Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
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TLDR
In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.Abstract:Â
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.read more
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Journal ArticleDOI
Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node
Jun-Sik Yoon,Eui-Young Jeong,Chang-Ki Baek,Ye-Ram Kim,Jae-Ho Hong,Jeong-Soo Lee,Rock-Hyun Baek,Yoon-Ha Jeong +7 more
TL;DR: Using systematic TCAD-based RC calculation, this work suggests optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.
Journal ArticleDOI
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs
TL;DR: An optimal buffer insertion algorithm is applied to the TSV-aware 3-D wirelength distribution models and various prediction results on wirelength, delay, and power consumption of3-D ICs are presented.
Proceedings ArticleDOI
BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems
Amirhossein Mirhosseini,Mohammad Sadrosadati,Behnaz Soltani,Hamid Sarbazi-Azad,Thomas F. Wenisch +4 more
TL;DR: BiNoCHS is introduced, a reconfigurable voltage-scalable on-chip network for heterogeneous systems that improves CPU/GPU performance by 57% / 34% over a latency-optimized network under congested conditions, while improving CPU performance by 28% over high-bandwidth design in unloaded conditions.
Journal ArticleDOI
Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology
TL;DR: In this paper, the authors show that the nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanwires that are higher up in the stack.
Journal ArticleDOI
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells
Moon Seok Kim,William Cane-Wissing,Xueqing Li,Jack Sampson,Suman Datta,Sumeet Kumar Gupta,Vijaykrishnan Narayanan +6 more
TL;DR: This article investigates and compares the layouts and parasitic capacitances and resistances of HVTFETs with FinFETs, and modeled the analytical parasitics in SPICE in order to analyze the impact of Parasitics.
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