Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Patent
Lookup engine with programmable memory topology
TL;DR: In this paper, an architecture for a specialized electronic computer for high-speed data lookup employs a set of tiles each with independent processors and lookup memory portions, which can be programmed to interconnect to form different memory topologies optimized for the particular task.
Journal Article
RFU Based Computational Unit Design For Reconfigurable Processors
TL;DR: In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores and a high gain in performance has been observed as compared to the conventional computing systems.
Book ChapterDOI
Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric 1
Colin J. Ihrig,Mustafa Baz,Justin Stander,Raymond R. Hoare,Oleg A. Prokopyev,Brady Hunsaker,Alex K. Jones +6 more
TL;DR: This book chapter describes several greedy heuristics for mapping large data-flow graphs (DFGs) onto a stripe-based coarse-grained reconfigurable fabric and introduces randomness into the heuristic to make decisions along the priority list.
Proceedings ArticleDOI
Mapping SoC architecture Solutions for an Application based on PACM Model
TL;DR: An approach for rapid embedded system prototyping using a generic high level architectural model and existing prototyping platforms and a several architecture prototype are proposed to rapid converge to a limed architecture space solutions.
Static resource models for code generation of embedded processors
TL;DR: The final author version and the galley proof are versions of the publication after peer review that features the final layout of the paper including the volume, issue and page numbers.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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