Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging
TL;DR: This work proposes a coarse-grain dynamic reconfigurable array, tightly coupled to a traditional RISC machine, taking advantage of using combinational logic to speed up the execution, and dynamic analysis of the code at run time was implemented to reconfigure the array, maintaining full software compatibility.
FPGA-Based System Virtual Machines
TL;DR: This thesis proposes to combine those reconfigurable areas with the idea of system virtual machines to combine a FPGA based virtualization system over conventional virtualization systems.
Proceedings Article
A methodology for hardware tasks scheduling optimized in time for partial and dynamic reconfiguration of fpgas
Remy Eskinazi,Manoel Eusebio de Lima,Paulo Maciel,Carlos Valderrama,Abel Guilhermino da Silva Filho,Paulo Sérgio B. Nascimento +5 more
TL;DR: This paper outlines the basic compiler data dependence analyses approaches that can be used to uncover reuse opportunities within a loop nest and describes the challenges of exploiting these opportunities in modern FPGAs.
Patent
Data transfer mechanism using unidirectional pull bus and push bus
TL;DR: In this article, the authors propose a method for transferring data between programming agents and memory resources, which includes data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus.
Dissertation
Configuration and data scheduling techniques for executing dynamic applications onto multicontext reconfigurable systems
TL;DR: In this paper, a planificación of aplicaciones dinamicas in arquitectures reconfigurables multi-contexto is discussed. But the authors focus on the scheduling of dynamic applications onto a multicontext coarse-grained reconfigurable architecture.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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