Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Dissertation
Partitionnement en ligne d'applications flots de données pour des architectures temps réel auto-adaptatives
TL;DR: In this paper, the authors propose an approche permettant d'allouer et d'ordonnancer dynamiquement les tâches d'une application flot de donnees en fonction d'un estimation de leurs temps d'execution afin de respecter les contraintes de temps.
Proceedings ArticleDOI
Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs
TL;DR: The preliminary results demonstrate that the optimized memory architecture is very effective in reducing kernel execution times (23.5% compared to a more straightforward alternative), and the approach can reduce the RA control overhead and other sequential code execution time in kernels significantly, resulting in up to 23.1% reduction in kernel execution time.
Patent
Queue arrays in network devices
TL;DR: In this article, a queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointed to the last element in the queue is stored in memory, and in response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation.
Proceedings ArticleDOI
Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor
TL;DR: A performance-oriented cost-driven algorithm for coarse-grained configuration prefetching is proposed that outperforms the probability-driven predictor by 10.8% to 29.6% in reducing reconfiguration overhead.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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