Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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TL;DR: In this paper, a bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses is presented, and Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.
Book ChapterDOI
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
Paul Graham,Brent Nelson +1 more
TL;DR: This paper discusses how this integration might be done and the potential area costs and performance benefits of incorporating RL onto a DSP chip, and proposes a reconfigurable coprocessor that can provide speed-ups ranging from 2-32x with an area cost of about a second DSP core.
Patent
Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator
TL;DR: In this article, the authors describe systems, methods, and apparatuses relating to a sequencer dataflow operator of a configurable spatial accelerator, where an interconnect network between a plurality of processing elements receives an input of a dataflow graph comprising of nodes forming a loop construct.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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