Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
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Patent
Write queue descriptor count instruction for high speed queuing
TL;DR: A write queue descriptor count command as discussed by the authors causes a processor to write a single word containing a queue count for each of a plurality of queue entries in a queue array cache, for high speed queuing.
Proceedings ArticleDOI
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring
Neetu Jindal,Sandeep Chandran,Preeti Ranjan Panda,Sanjiva Prasad,Abhay Mitra,Kunal Singhal,Shubham Gupta,Shikhar Tuli +7 more
TL;DR: This work proposes DHOOM, an architectural framework for runtime monitoring of program assertions, which exploits the combination of a reconfigurable fabric present alongside a processor core with the vestigial on-chip Design-for-Debug hardware to minimize the overall performance overhead of runtime verification.
Patent
System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration
Andreas Doering,Silvio Dragone,Andreas Herkersdorf,Richard Gerard Hofmann,Charles Edward Kuhlmann +4 more
TL;DR: In this article, a method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor coupled to a processor is presented, where the FPGA can be programmable dynamically during the execution of an application.
Journal ArticleDOI
Custom wide counterflow pipelines for high-performance embedded applications
TL;DR: A new CFP architecture is described, called the wide counterflow pipeline (WCFP), that extends the original proposal to be better suited for custom embedded instruction-level parallel processors and shows that custom WCFPs have performance that is up to four times better than that of ASIPs based on the CFP.
Book ChapterDOI
ERA – Embedded Reconfigurable Architectures
Stephan Wong,Luigi Carro,Mateus Beck Rutzig,Debora Matos,Roberto Giorgi,Nikola Puzovic,Stefanos Kaxiras,Marcelo Cintra,Giuseppe Desoli,Paolo Gai,Sally A. McKee,Ayal Zaks +11 more
TL;DR: The focus of the ERA project is to investigate and propose new methodologies in both tools and hardware design to break through the power and memory walls, and help design the next-generation embedded systems platforms.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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