Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Book ChapterDOI
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems
TL;DR: This paper will propose a new dynamically reconfigurable network, dedicated to data oriented applications such as the one allowed on third generation networks, and principles, realizations and comparative results will be exposed for some classical applications targeted on different architectures.
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VLSI architecture of the reconfigurable computing engine for digital signal processing applications
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TL;DR: The kernel component of the reconfigurable computing (RC) engine is the general-purpose processing cluster (GPPC) array, which is constructed of the GPPCs, as an MIMD model to achieve high flexibility for mapping applications and algorithms to the RC engine.
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A Dynamic Retargettable Multi-Protocol RFID Reader/Writer
TL;DR: A novel RFID reader/writer architecture that dynamically retargets various protocols of RFID by changing configuration software is proposed, which consumes lower power than that of software defined radio, because the proposed architecture does not require high performance CPUs.
Patent
Memory circuits and methods for distributed memory hazard detection and error recovery
TL;DR: In this article, a memory circuit includes a memory interface circuit to service memory requests from a spatial array of processing elements for data stored in a plurality of cache banks, and a hazard detection circuit in each of the plurality of caches.
Proceedings ArticleDOI
An efficient configuration unit design for VLIW based reconfigurable processors
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TL;DR: The presented configuration unit design is capable of loading the minimum configuration streams with the most optimal configuration overheads and hence it leads to a dramatic enhancement in the performance of reconfigurable processor.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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