Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG
TL;DR: A fundamentally new approach that first makes the architecture more flexible and exposes this flexibility to the compiler and enables the performance of auto-acceleration to be comparable to that of manually-optimized implementations is taken.
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Robox: an end-to-end solution to accelerate autonomous control in robotics
TL;DR: RoboX is created, an end-to-end solution which exposes a high-level domain-specific language to roboticists which allows roboticists to express the physics of the robot and its task in a form close to its concise mathematical expressions.
Journal ArticleDOI
Fast and compact sequential circuits for the FPGA-based reconfigurable systems
TL;DR: A new sequential circuit synthesis methodology is discussed that targets LUT FPGAs and FPGA-based reconfigurable system-on-a-chip platforms and demonstrates that the information-driven approach consistently applied in the whole sequential Circuit synthesis chain efficiently produces very fast and compact sequential circuits.
Proceedings ArticleDOI
Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation
Chen-Han Hoy,Venkatraman Govindarajuz,Tony Nowatzki,Ranjini Nagaraju,Zachary Marzecy,Preeti Agarwal,Chris Frericks,Ryan Cofell,Karthikeyan Sankaralingam +8 more
TL;DR: The experience of bringing up an end-to-end prototype of an ISA-exposed accelerator has made clear that two particular artifacts are greatly needed to perform this type of design more quickly and effectively: Open-source implementations of high-performance baseline processors, and Declarative tools for quickly specifying combinations of known compiler transforms.
Proceedings ArticleDOI
DynaSpAM: dynamic spatial architecture mapping using out of order instruction schedules
TL;DR: The insight behind DynaSpAM is that today's powerful OOO processors do for themselves most of the work necessary to produce a highly optimized mapping for a spatial architecture, including aggressively speculating control and memory dependences, and scheduling instructions using a large window.
References
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Book
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Bruce Schneier,Phil Sutherland +1 more
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Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
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Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
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Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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