scispace - formally typeset
Proceedings ArticleDOI

Garp: a MIPS processor with a reconfigurable coprocessor

Reads0
Chats0
TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Abstract
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

read more

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI

Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor

TL;DR: The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.
Proceedings ArticleDOI

A quantitative analysis of the speedup factors of FPGAs over processors

TL;DR: A deeper understanding of the tradeoff between system complexity and performance when designing Configurable SoC as well as designing software for CSoC is provided and the one to two orders of magnitude in speedup of FPGAs over CPU after accounting for clock frequencies is understood.
Proceedings ArticleDOI

NAPA C: compiling for a hybrid RISC/FPGA architecture

TL;DR: The NAPA C language as mentioned in this paper is a pragma-based approach to programming hybrid devices that allows the programmer to specify where data is to reside and where computation is to occur with statement-level granularity.
Proceedings ArticleDOI

The NAPA adaptive processing architecture

TL;DR: The technical aspects of the architecture are emphasized to achieve the first goal while illustrating key architectural concepts motivated by the second and third goals.
Patent

Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity

TL;DR: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity, is presented in this article.
References
More filters
Book

Applied Cryptography: Protocols, Algorithms, and Source Code in C

TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Book

Digital Halftoning

Proceedings ArticleDOI

A high-performance microarchitecture with hardware-programmable functional units

TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation

Reconfigurable Architectures for General-Purpose Computing

TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI

Processor reconfiguration through instruction-set metamorphosis

TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
Related Papers (5)