Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
Reads0
Chats0
TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
More filters
Patent
Processing a data packet
Donald Hooper,Mark B. Rosenbluth,Gilbert Wolrich,Matthew J. Adiletta,Hugh Wilkinson,Robert J. Kushlis +5 more
TL;DR: In this paper, the authors describe a method for processing a data packet at a device and determine available memory in one or more of the local memories of a plurality of execution threads.
Book ChapterDOI
A High-Performance Flexible Architecture for Cryptography
TL;DR: This paper describes how various proposed AES algorithms could be implemented on PipeRench, a reconfigurable fabric that supports implementations which can yield better than custom-hardware performance and yet maintains all the flexibility of software based systems.
Journal ArticleDOI
A polymorphous computing fabric
C. Wolinski,M. Gokhale,K. McCave +2 more
TL;DR: A polymorphous computing fabric-based system (FBS) well suited to digital signal processing (DSP) and image processing applications and implemented on a system on a programmable chip (SoPC).
Book ChapterDOI
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
TL;DR: A compiler directed approach to hiding the configuration loading latency is presented and it is shown that the Chameleon CS2112 chip performance is significantly improved by leveraging such compiler and multithreading techniques.
Book ChapterDOI
The Instruction-Set Extension Problem: A Survey
Carlo Galuzzi,Koen Bertels +1 more
TL;DR: The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application and compensate the lack of a general view of the problem in the existing literature.
References
More filters
Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
Related Papers (5)
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more