Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Coarse grain reconfigurable architecture (embedded tutorial)
TL;DR: The paper gives a brief survey over a decade of R&D on coarse grain reconfigured hardware and related compilation techniques and points out its significance to the emerging discipline of reconfigurable computing.
Journal ArticleDOI
Energy savings and speedups from partitioning critical software loops to hardware in embedded systems
TL;DR: These experiments represent the most comprehensive hardware/software partitioning study published to date and found that moving critical code to hardware resulted in average speedups of 3 to 5 and average energy savings of 35% to 70%, with average hardware requirements of only 5000 to 10,000 gates.
Journal ArticleDOI
The Instruction-Set Extension Problem: A Survey
Carlo Galuzzi,Koen Bertels +1 more
TL;DR: A thorough analysis of the issues involved during the customization of an instruction-set by means of a set of specialized application-specific instructions is presented.
Book ChapterDOI
Instruction-Level Parallelism for Reconfigurable Computing
TL;DR: This paper will review techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors in their original context, describe how they have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language.
Proceedings ArticleDOI
Bundled execution of recurring traces for energy-efficient general purpose processing
TL;DR: This approach identifies recurring instruction sequences as phases of “temporal regularity” in a program's execution, and maps suitable ones to the BERET hardware, a three-stage pipeline with a bundled execution model that demonstrates significant savings on instruction fetch, decode and register file accesses energy.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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