Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Book ChapterDOI
Modeling and Analysis for Reconfigurable Cell Based on Stochastic Petri Net
TL;DR: This paper proposes a method to model the reconfigurable cell based on stochastic Petri net, and discusses the effects between dynamic reconfiguration time and task response time under three different conditions.
Dissertation
Rtrassoc51 - módulo de pipeline para um processador com arquitetura harvard superescalar embarcado (pahse)
TL;DR: PAHSE was implemented in VHDL and simulation results, as well as, proposed future are presented in the end of this dissertation.
Patent
Bus systems and reconfiguration method
TL;DR: In this article, the authors present a control method for reconfiguration of reconfigurable elements effected via control signals transmitted together with data and/or trigger signals, e.g. using bus switches.
Journal ArticleDOI
FPGA-extended Modified Harvard Architecture
TL;DR: The main contribution is the introduction of the “FPGA-extended modified Harvard architecture” model to enable software-transparent context-switching between processes with a different distribution of instructions.
Journal Article
Module Mapping Algorithm for Reconfigurable Computing System
TL;DR: A module mapping algorithm based on dynamic partial reconfigurable technology for sequential applications that utilizes the high effectiveness and flexibility of dynamic reconfiguration to hide the configuration time so that the program execution time can be reduced and the system performance is improved.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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