Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
Reads0
Chats0
TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
More filters
Dissertation
Reconfiguration of field programmable logic in embedded systems
TL;DR: This thesis presents a set of techniques for evaluating and exploiting the programmability of a reconfigurable computing fabric in embedded systems and exploits static and medium frequency reconfiguration by exploiting inter-task mutually exclusive resource usage.
Dissertation
Evolve : a preliminary multicore architecture for Introspective Computing
TL;DR: This thesis work develops two Partner Cores software systems: the Dynamic Partner-Assisted Branch Predictor and the Introspective L2 Memory System (IL2), which employs a partner core as a coprocessor engine for general dynamic branch prediction in a corresponding code core.
Proceedings ArticleDOI
RtrASSoc: an adaptable superscalar reconfigurable system-on-chip. The simulator
TL;DR: RtrASSoc as discussed by the authors is an Adaptable, Superscalar and Reconfigurable System on Chip (RSOC) based on Programmable System-on-Chip (PSOC).
Book
Hardware Virtualization on a Coarse-Grained Reconfigurable Processor
TL;DR: It is argued that a reconfigurable processor with a coarse-grained, dynamically reconfiguring array of modest size provides an attractive implementation platform for the authors' application domain and that hardware virtualization on the Zippy architecture is feasible and enables us to trade-off performance for area in embedded systems.
References
More filters
Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
Related Papers (5)
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more