Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Out-of-order execution on reconfigurable heterogeneous MPSOC using particle swarm optimization
T. Selvameena,R. Arun Prasath +1 more
TL;DR: In this paper, modified score boarding algorithm is used along with particle swarm optimization technique Particle swarm optimization improves the efficiency and performance in the prototyped field programmable gate array (FPGA) fabric is composed of both software based static and dynamic implementation on top of a heterogeneous MPSOC.
Proceedings ArticleDOI
Customization methodology of a Coarse Grained Reconfigurable architecture
TL;DR: A tool that takes the hardware configuration of a set of applications, identifies the unused parts of the CGRA, and let the user sweep the design space from fully programmable to fully customized by eliminating the unused components is introduced.
Proceedings ArticleDOI
Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor
K.s. Tham,Douglas L. Maskell +1 more
TL;DR: A simulation framework using a software-oriented design methodology that can be adopted to model the software and hardware components in a reconfigurable co-processor and shows that hardware-software trade-offs in the various models can be efficiently analyzed during the initial design phase.
Hardware Support for Dynamic Partial Reconfiguration
TL;DR: This thesis describes a generic approach for Dynamic Partial Reconfiguration (DPR) of a reconfigurable platform, connected to a general purpose system through a high-speed interconnect, that can dynamically install and execute hardware instances of software functions (bitstreams) on-demand.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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