Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
Like Yan,Gang Wang,Tianzhou Chen +2 more
TL;DR: Focusing on the area and performance balance, a dynamically adaptive reconfigurable accelerator framework is proposed on CPU/RA architecture in the paper and a bzip2 case study is presented, the experimental results demonstrated the feasibility of the approach, and shown that up to 93.6% reconfigured area is saved at a cost of 1.
Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration
TL;DR: This work designed and evaluated a transparent binary acceleration approach, targeting Field Programmable Gate Array devices, which relies on instruction traces to automatically generate specialized accelerator instances, and which is capable of expediently generating accelerator-augmented embedded systems which achieve considerable performance increases whilst incurring a low resource cost, and without requiring manual hardware design.
Patent
Processor chip including a plurality of cache elements connected to a plurality of processor cores
Martin Vorbach,Armin Nückel +1 more
TL;DR: In this paper, the authors present a programming of modules which can be reprogrammed during operation, and a partitioning of code sequences is also described, based on the notion of code sequence partitioning.
Fast design space exploration for low-power configurable processors
TL;DR: This dissertation presents new methods of design space exploration and fast architecture evaluation and a fast performance estimation approach is proposed for evaluating configurations of instruction-set extensions to improve the automation and usability of ASIPs.
Proceedings ArticleDOI
A parallel implementation of MP3 decoding algorithm on Reconfigurable Computing systems
TL;DR: A novel mapping mechanism which makes data-Parallelism instructions operate on RCA has been proposed to map and implement MP3 audio decoding algorithm containing intrinsic data-parallelism operations.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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