Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Burst mode: a new acceleration mode for 128-bit block ciphers
TL;DR: Investigation of the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher, raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.
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Compiling to FPGAs via an EPIC compiler's intermediate representation
TL;DR: This paper presents an approach to compile a system level description to hardware through a conventional software intermediate representation (IR) of a state-of-the-art optimizing compiler for Explicitly Parallel Instruction Computing (EPIC) processors.
Book ChapterDOI
Evaluating the performance of space plasma simulations using FPGA's
Ben Popoola,Paul Gough +1 more
TL;DR: This paper analyses the performance of a custom compute machine, that performs electrostatic plasma simulations, using Field Programmable Gate Array's (FPGAs), and describes the development of the architecture and its support for the C-programming language via the use of a cross-compiler.
Proceedings Article
Improving Performance and Quality thru Hardware Reconfiguration: Potentials and Adaptive Object Tracking Case Study.
TL;DR: The issues involved in using reconfigurable hardware devices for multimedia applications are discussed, and the ideas and approach are then applied to a collaborative object tracking system that has been built as part of this work.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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