Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Book ChapterDOI
Stream Computations Organized for Reconfigurable Execution (SCORE)
TL;DR: This abstract introduces SCORE (Stream Computation Organized for Reconfigurable Execution), a stream-based compute model which virtualizes reconfigurable computing resources (compute, storage, and communication) by dividing a computation up into fixed-size "pages" and time-multiplexing the virtual pages on available physical hardware.
Proceedings ArticleDOI
Design patterns for reconfigurable computing
André DeHon,Joshua Adams,Michael deLorimier,Nachiket Kapre,Y. Matsuda,Helia Naeimi,M. Vanier,Michael G. Wrighton +7 more
TL;DR: This role for design patterns in reconfigurable computing is articulated, a few example patterns are provided, a starting point for the contents of the catalog is offered, and the potential benefits of this effort are discussed.
Journal ArticleDOI
A VLIW processor with reconfigurable instruction set for embedded applications
TL;DR: A new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath, leading to an improvement in both timing performance and power consumption.
Proceedings ArticleDOI
Adapting software pipelining for reconfigurable computing
TL;DR: This paper presents a simple, uniform schema for pipelined the hardware execution of a broad class of loops, which resembles VLIW software pipelining much more than it resembles hardware synthesis retiming algorithms.
Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial
TL;DR: This paper introduces SCORE (Stream Computation Organized for Reconfigurable Execution), a streambased compute model which virtualizes reconfigurable computing resources (compute, storage, and communication) by dividing a computation up into fixed-size “pages” and time-multiplexing the virtual pages on available physical hardware.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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