Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Book ChapterDOI
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays
TL;DR: Simulations have shown that even a comparatively simple and compact extension of a conventional hardwired microprocessor with a reconfigurable logic array allows performance gains of 2–4 times over conventional RISC processors of comparable complexity, making this approach especially interesting for embedded microprocessors.
Patent
Semiconductor integrated circuits, data transfer systems, and the method for data transfer
TL;DR: In this article, a semiconductor integrated circuit configured for connection to an external ROM includes a decryption code block, a decoder circuit, a configuration circuit, and an internal circuit connected to the FPGA circuit.
Applications of reprogrammability in algorithm acceleration
TL;DR: This doctoral thesis consists of an introductory part and eight appended publications, which deal with hardware–based reprogrammability in algorithm acceleration with a specific emphasis on the possibilities offered by modern large–scale Field Programmable Gate Arrays in computationally demanding applications.
The Case for High Level Programming Models for Reconfigurable Computers.
David L. Andrews,Ron Sass,Erik K. Anderson,Jason Agron,W. Peck,Jim Stevens,Fabrice Baijot,Ed Komp +7 more
TL;DR: The need for researchers to develop new high-level programming models, and not just focus on extensions to programming languages, for enabling accessibility and portability of standard high level applications across the CPU/FPGA boundary is discussed.
Dynamically reconfigurable bio-inspired hardware
Upegui Posada,Andres Emilio +1 more
TL;DR: This thesis presents a set of architectures, techniques, and methodologies for benefiting from the configurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems, and proposes several adaptation techniques for parametric and topological adaptation.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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