Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Patent
Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
Martin Vorbach,Robert Münch +1 more
TL;DR: In this article, an expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations, which greatly reduces the volume of data required for configuration.
Patent
Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
TL;DR: In this paper, a configurable spatial accelerator includes a plurality of processing elements, a circuit switched interconnect network between the plurality of nodes to receive an input of a dataflow graph comprising a plurality nodes, and a controller that switches the in-network storage element into a first mode that provides a value stored in the queue of the storage element by the output queue of a processing element to an input queue of another processing element when a configuration value is a first value.
Journal Article
Stream computations Organized for reconfigurable execution (SCORE): Extended abstract
TL;DR: SCORE as mentioned in this paper is a stream-based model for reconfigurable computing, which divides a computation up into fixed-size pages and time-multiplexes the virtual pages on available physical hardware.
Embedded Processor based System Design: A Brief Overview
Divakar Tamang,O.P. Roy +1 more
TL;DR: General aspects of embedded systems are described, their status and future market trends are analyzed, and the present design trends with difference between embedded processor and desktop processor are explained.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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