Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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ACRES Architecture and Compilation
TL;DR: The ACRES (Architecture and Compiler for REconfigurable Systems) platform that combines the flexibility of a programmable technology and the efficiency of custom hardware without incurring high-cost, high-risk chip development is described.
Patent
Providing real-time control data for a network processor
TL;DR: In this article, the push engine performs unsolicited transfers of a portion of the status data to the processing engines in response to the module collecting new status data, indicating readiness of the devices to participate in data transfers over the bus.
Dissertation
Déploiement d'applications multimédia sur architecture reconfigurable à gros grain : modélisation avec la programmation par contraintes
TL;DR: Cette methodologie nous a permis, grâce a la CP, de modeliser et de resoudre un ensemble of problemes combinatoires complexes, aux problematiques de conception et de compilation d’applications pour CGRA.
Journal ArticleDOI
Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators
Siyuan Xu,Shuangnan Liu,Yidi Liu,Anushree Mahapatra,Monica Villaverde,Felix Moreno,Benjamin Carrion Schafer +6 more
TL;DR: Three different methods to automatically characterize heterogeneous MPSoCs composed of a variable number of masters and hardware accelerators (HWaccs) are proposed, based on cycle-accurate simulations of the complete MPSoC and on a Configurable SoC FPGA.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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