Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Book ChapterDOI
A Web-Based Multiuser Operating System for Reconfiguarble Computing
TL;DR: A multitasking operating system to share the authors' SPACE.2 coprocessing board among up to 8 simultaneous users and a suite of pre-configured tasks and a web based client allows novices to run reconfigurable computing applications.
Patent
Multi-core processing system
TL;DR: In this paper, a cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell mean for receiving, storing and or outputting information is described.
Patent
Method and system for handling an instruction not supported in a coprocessor formed using configurable logic
TL;DR: In this article, the authors describe a method of informing a processor that a coprocessor instruction is not executable by the processor via a controller, which queries control logic to determine whether the processor is configured to execute the instruction.
Proceedings ArticleDOI
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
Anne Bracy,Amir Roth +1 more
TL;DR: To reconcile the seemingly conflicting goals of resource amplification and serialization avoidance, this paper develops three schemes that identify and reject mini-graphs with harmful serialization, including slack-profile, which virtually eliminates serialization-induced slowdowns while providing 34% amplification rates.
Patent
Multiple calendar schedule reservation structure and method
Donald Hooper,Suresh S. Kalkunte +1 more
TL;DR: In this article, a machine-based method includes scheduling data units into respective time slots of reservation groups by representing the time slots in a base vector and each of the reservation groups corresponds to a contiguous block in the base vector.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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