Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Journal ArticleDOI
Selecting profitable custom instructions for reconfigurable processors
TL;DR: A practical computing model is proposed for the custom-instruction selection problem that takes into account the area constraint of the reconfigurable fabric and two heuristic algorithms and an exact algorithm are proposed.
Book ChapterDOI
Dynamically Adapted Low Power ASIPs
TL;DR: An ASIP reconfigurable development flow that aggregates design area optimization and a run-time technique that reduces energy consumption is proposed that builds an area optimized reconfigured architecture to provide a high-performance and energy-efficient execution of a defined application set.
Patent
Chip including memory element storing higher level memory data on a page by page basis
TL;DR: In this article, a bus system for transferring data between parts of a multiprocessor system is presented, where each segment is controlled by a table providing routing information, where the data includes an identifier that identifies the source of the data transfer and/or the target of data transfer.
Unifying software and hardware of multithreaded reconfigurable applications within operating system processes
TL;DR: A unified Operating System (OS) process for codesigned reconfigurable applications is introduced that provides unified memory abstraction for software and hardware application parts, and runtime optimisations in the system layer supporting the unified OS process can minimise the performance loss and even outperform typical approaches.
Proceedings ArticleDOI
A three-dimensional FPGA with an integrated memory for in-application reconfiguration data
S.M.S.A. Chiricescu,M.M. Vai +1 more
TL;DR: This FPGA architecture is based on a novel 3-D VLSI circuit technology developed at Northeastern University and a new interconnection scheme as well as a new reconfiguration mechanism are features of the architecture.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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