Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Journal ArticleDOI
Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
Dissertation
Compiling stream applications for heterogeneous architectures
Scott Mahlke,Amir Hormati +1 more
TL;DR: This work introduces a hybrid flexible compilation framework that facilitates dynamic adaption of applications to the changing characteristics of the underlying architecture and introduces several compiler optimizations that facilitate portability and retargetability while achieving high performance.
Proceedings ArticleDOI
A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays
TL;DR: The results show that the proposed algorithm significantly improves the routability and total wire-length of the mapped configuration sets, with results ranging from 21% to 55% for various quality metrics.
Proceedings ArticleDOI
Reconfiguration Cost for Reconfigurable Computing Architectures
TL;DR: In this paper , the cost of typical reconfiguration techniques which can be applied to not only field-programmable gate arrays (FPGAs) but also coarse-grained reconfigurable arrays (CGRAs).
Journal ArticleDOI
Reconfiguration Cost for Reconfigurable Computing Architectures
Shigeyuki Takano,Hideharu Amano +1 more
TL;DR: The cost of typical reconfiguration techniques can be applied to not only field-programmable gate arrays (FPGAs) but also coarse-grained reconfigurable arrays (CGRAs) as mentioned in this paper .
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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