Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Dissertation
Framework for a Context-Switching Run-Time Reconfigurable System
TL;DR: This thesis discusses the development of a framework to support applications which execute on a run-time reconfigurable system containing context-switching devices, divided into a number of layers: hardware, middleware, software, and applications.
Proceedings ArticleDOI
Optimization and evaluation of the reconfigurable Grid Alu Processor
TL;DR: Evaluating the GAP architecture and optimizing the hardware, the number of FUs, and the configuration layers implemented in the array shows a significant speed up for sequential applications on GAP in comparison to an out-of-order superscalar simulator.
Architectural and scalability issues in hardware synthesis of high-level languages Qualifying Dissertation
TL;DR: This document examines the use of FPGAs as an implementation platform and how they are related to the system-on-chip and network- on-chip design methodologies and discusses the current state of hardware synthesis and examines the problems that are encountered when using it.
Journal Article
Increasing ILP of RISC microprocessors through control-flow based reconfiguration
TL;DR: First experiments executing DSP algorithms have indicated, that the proposed architecture can exploit more of the potential application parallelism than conventional VLIW processors.
Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms
TL;DR: In this article, the use of digital communication systems has increased in such a way that network bandwidth is affected, and this problem can be solved by implemening the network.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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