Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Journal ArticleDOI
Design of a Reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms
TL;DR: A reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper and can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP.
Proceedings Article
Evaluation of Run-Time Reconfiguration for General-Purpose Computing.
TL;DR: In order to investigate the impact of dynamic hardware reconfiguration on general-purpose applications, a superscalar micro-architecture that includes a variable number of execution units is presented that is based on the run-time behaviour of the application.
Proceedings ArticleDOI
Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph
TL;DR: A stochastic memory partitioning scheme based on the well-known simulated annealing algorithm is proposed that outperforms A2 and A1 by 34% and 250%, respectively, and is evaluated against two other DLM architecture synthesizing methods.
Proceedings ArticleDOI
Design of steering vectors for dynamically reconfigurable architectures
TL;DR: This study reveals that it is often possible for the architecture to closely track ideal desired configurations even when K is relatively small, which can increase the number of configurations that the architecture can reach, but at the expense of more hardware complexity to construct the busses.
Goal-Driven Reconfiguration of Polymorphous Architectures
TL;DR: A heuristic framework for guiding the runtime configuration adaptation process is developed, and it is shown that this approach can efficiently handle both dynamics in performance requirements and in task execution times.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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