Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
Reads0
Chats0
TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
More filters
Dissertation
High-level compilation for gate-reconfigurable architectures
Jonathan Babb,Anant Agarwal +1 more
TL;DR: This dissertation solves this fundamental problem of gate-reconfigurable architectures by specializing architectural mechanisms with respect to input programs by integrating the techniques of high-level synthesis with the static routing concepts developed for single-chip multiprocessors.
Proceedings ArticleDOI
Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors
TL;DR: The simulation and FPGA implementation results prove that the additional hardware access latencies in the processor are tolerated by the SVP architecture, and the Thread Mapping Table unit allows to realize the coupling scheme seamlessly without modifications of the processor ISA.
Proceedings ArticleDOI
Design and Analysis of Interconnection Network of Reconfigurable Cryptographic Processor
TL;DR: Several conceptions such as connectivity, network width, network scale have been proposed, some design principles of the interconnection network have been given, three typical interconnection networks named all interconnected, single bus, multiple bus have been introduced and their features have been analyzed.
Proceedings ArticleDOI
Kernel formation in Garpcc
TL;DR: The Garp project quantitatively investigates the benefits of adding an on-chip dynamically reconfigurable coprocessor to a standard instruction processor for acceleration of loops, and the companion project Garpcc investigates whether new compilation approaches can enable automatic exploitation of the cop rocessor starting from standard C code.
Dissertation
Correct synthesis and integration of compiler-generated function units
TL;DR: This thesis introduces an approach to reasoning about the correctness of compilers that generate custom logic that can be synthesized to provide hardware acceleration for a given application.
References
More filters
Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
Related Papers (5)
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more