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Proceedings ArticleDOI

Garp: a MIPS processor with a reconfigurable coprocessor

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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Abstract
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

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Citations
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Proceedings ArticleDOI

A hybrid processing element based reconfigurable architecture for hashing algorithms

TL;DR: This paper introduces a methodology to derive hybrid grained processing elements and expose both fine and coarse grain parallelism based on a new common and recurring computation pattern extraction tool and presents a case-study to show that application- specific reconfigurable computing has performance benefits close to fully-custom designs in addition to the intended reconfigurability.
Journal ArticleDOI

A reconfigurable processor architecture combining multi-core and reconfigurable processing units

TL;DR: A Reconfigurable Multi-Core (RMC) architecture combining general multi- core and reconfigurable logic is proposed, which shows a 3.10 times average speedup over software implementation on the original multi-core, and the data and control communication overhead on RMC is acceptable.
Dissertation

The Kiel Esterel processor: a multi-threaded reactive processor

Xin Li
TL;DR: This thesis presents the Kiel Esterel Processor (KEP), the multi-threaded reactive architecture is responsible for managing the control flow of all threads, and the KEP Instruction Set Architecture is complete in that it allows a direct mapping of all EstereL statements onto KEP assembler.
Book ChapterDOI

Hardware Technology and Programming Languages for Reconfigurable Devices

TL;DR: This chapter presents an overview of hardware description languages for reconfigurable devices from lower-level languages like VHDL and Verilog to higher-level C-based languages and contains an introduction to the Handel-C programming language.
References
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Book

Applied Cryptography: Protocols, Algorithms, and Source Code in C

TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Book

Digital Halftoning

Proceedings ArticleDOI

A high-performance microarchitecture with hardware-programmable functional units

TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation

Reconfigurable Architectures for General-Purpose Computing

TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI

Processor reconfiguration through instruction-set metamorphosis

TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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