Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
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Proceedings ArticleDOI
PRAM: a novel model for 2-dimensional reconfigurable arrays
TL;DR: A generic parameterized model (PRAM) for reconfigurable architecture is presented and an architecture description language (RADL) is proposed that is able to describe complex, heterogeneous and multi-granularity architectures.
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Optimization of behavioral IPs in multi-processor system-on-chips
TL;DR: This work introduces a method to automatically identify the workload of each behavioral IP mapped as a slave on an MPSoC system and re-synthesizes it to maximize its efficiency, i.e. reduce its area and minimize its idle time, without affecting the overall performance.
Dissertation
Approche multicouches pour la reconfigurabilité de systèmes de communications de 3ème génération
TL;DR: In this paper, a nouvelle methode de reconfigurabilite appelee "Approche iterative" is proposed, which can be used to optimize conjointement the performance and the consommation de puissance lors d'un changement du canal de propagation or des parametres de communication.
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The SOBER Family Ciphers Reconfigurable Processing Architecture Design
TL;DR: The reconfigurable processing architecture design for SOBER family ciphers is introduced and it is proved by experiment that it uses fewer hardware resources and it’s process speed can achieve W*100M bits/s.
Flexible and efficient accelerator architecture for runtime monitoring
TL;DR: This thesis will describe steps to build an architectural framework for run-time monitoring that can address the drawbacks of previously proposed run- time monitoring schemes by utilizing reconfigurable hardware and optimizing for performance.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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