Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Reconfigurable instruction set processors: a survey
F. Barat,Rudy Lauwereins +1 more
TL;DR: The different hardware aspects that have to be considered during the design of a reconfigurable instruction-set processor, including the coupling of the processor and the reconfigured logic, the configuration, instruction coding and scheduling, granularity, the hardware cache and reconfigurability are discussed.
Proceedings ArticleDOI
An evolvable hardware FPGA for adaptive hardware
Pauline C. Haddow,Gunnar Tufte +1 more
TL;DR: The authors consider the characteristics of evolvable hardware, especially for adaptive design, and discuss the demands that these characteristics place on the underlying technology, and suggest a potential alternative to today's FPGA technology.
Book ChapterDOI
The MOLEN ρμ-Coded Processor
TL;DR: The MOLEN ρμ-coded processor as mentioned in this paper is a reconfigurable superscalar processor that includes fixed and pageable microcode hardware features to extend the flexibility and improve the performance.
Patent
Multithreaded microprocessor with register allocation based on number of active threads
TL;DR: In this article, the authors propose a mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use in a multi-threaded processor.
Journal ArticleDOI
A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective
TL;DR: There are ample opportunities for future research on Coarse-Grained Reconfigurable Architectures, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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