Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Scientific Application Acceleration with Reconfigurable Functional Units
TL;DR: This study analyzes application traces of Sandia's scientific applications and the SPEC-FP benchmark suite and uses execution-based simulation to determine the acceleration potential of the applications when using an RFU.
Proceedings ArticleDOI
Design of transport triggered architecture processors for wireless encryption
TL;DR: TTA processors for the RC4 and AES encryption algorithms of the new IEEE 802.11i WLAN security standard are designed and special operations efficiently supporting the ciphers are developed.
BookDOI
SPS: A strategically programmable system
TL;DR: Dedicated blocks fixed on the chip perform the bulk of the computations; hence the reconfiguration time of the system is highly improved as well other performance metrics such as speed and power consumption.
Patent
Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
Suresh S. Kalkunte,Donald Hooper +1 more
TL;DR: In this paper, a system and method for controlling transmission of cells is described, where the cells are associated with virtual circuits that either require shaping according to constant bit rate (CBR) or real-time variable bit rate, or no shaping with transmit selection based on priority (for services other than CBR and rt-VBR).
Patent
Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
TL;DR: In this paper, the authors describe methods and apparatuses relating to consistency in an accelerator, where request address file (RAF) circuits are coupled to a spatial array by a first network, and a memory is coupled to the RAF circuits by a second network, a request to the memory marked with a program order dependency on a previous request until receiving a first token generated by completion of the previous request to memory by another RAF circuit.
References
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Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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A high-performance microarchitecture with hardware-programmable functional units
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