Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Patent
Processor and pipeline reconfiguration control method
Shiro Uriu,Mitsuharu Wakayoshi,Tetsuo Kawano,Hiroshi Furukawa,Ichiro Kasama,Kazuaki Imafuku,Toshiaki Suzuki +6 more
TL;DR: In this paper, a reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends, and a counter compares the fixed clock cycle with the actual number of elapsed clocks.
Journal ArticleDOI
Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator
TL;DR: A cross-cutting approach to explore the design space to solve the channel estimation problem on reconfigurable devices with a focus on the matching pursuit algorithm, which is a fast and accurate iterative algorithm for multipath channel estimation.
Proceedings ArticleDOI
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits
Andy Ye,Jonathan Rose +1 more
TL;DR: A packing algorithm for the multi-bit logic block architecture is proposed in this paper and it is used to empirically find the best values for several important architectural parameters of the new architecture, including the most area efficient granularity values and themost area efficient amount of configuration memory sharing.
Patent
Processors, methods, and systems for a memory fence in a configurable spatial accelerator
TL;DR: In this article, the memory fence mechanism in a configurable spatial accelerator is described, where a processor includes a plurality of processing elements and an interconnect network between them to receive an input of a dataflow graph comprising of nodes, and a fence manager is also included to manage a memory fence between a first operation and a second operation.
Proceedings ArticleDOI
ECOMIPS: an economic MIPS CPU design on FPGA
TL;DR: This article introduces a MIPs CPU architecture or ECOMIPS to be implemented for economic resource utilization on modern chips (Xilinx Spartan 3 families) and tries to make itself a customizable and reusable architecture for bridging the gap between microprocessor and ASIC.
References
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Book
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Bruce Schneier,Phil Sutherland +1 more
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Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
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Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
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Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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