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Proceedings ArticleDOI

Garp: a MIPS processor with a reconfigurable coprocessor

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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Abstract
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

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Proceedings ArticleDOI

Exploiting operation level parallelism through dynamically reconfigurable datapaths

TL;DR: This work presents a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating co-processor and compares the efficiency of exploiting the operation level parallelism using classic VLIW processors and this proposed class of dynamically configurable co-processors.
Proceedings ArticleDOI

A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O

TL;DR: A system-chip targeting image and voice processing and recognition application domains that features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA.
Proceedings ArticleDOI

Reconfigurable computing: a new business model-and its impact on SoC design

TL;DR: Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream, and now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design.
Proceedings ArticleDOI

A reconfigurable multi-processor SoC for media applications

TL;DR: Simulation results show that the processing capability of REMUS is to support 1920⋆1088 @30fps videos at 200 MHz in real-time decoding of H.264 high-profile streams.
References
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TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Book

Digital Halftoning

Proceedings ArticleDOI

A high-performance microarchitecture with hardware-programmable functional units

TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation

Reconfigurable Architectures for General-Purpose Computing

TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI

Processor reconfiguration through instruction-set metamorphosis

TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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