Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
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TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
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Proceedings ArticleDOI
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Zhining Huang,M. Sharad +1 more
TL;DR: This work presents a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating co-processor and compares the efficiency of exploiting the operation level parallelism using classic VLIW processors and this proposed class of dynamically configurable co-processors.
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A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O
TL;DR: A system-chip targeting image and voice processing and recognition application domains that features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA.
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Reconfigurable computing: a new business model-and its impact on SoC design
TL;DR: Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream, and now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design.
Proceedings ArticleDOI
A reconfigurable multi-processor SoC for media applications
TL;DR: Simulation results show that the processing capability of REMUS is to support 1920⋆1088 @30fps videos at 200 MHz in real-time decoding of H.264 high-profile streams.
References
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Book
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Bruce Schneier,Phil Sutherland +1 more
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Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
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Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
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Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
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