Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
- pp 12-21
Reads0
Chats0
TLDR
Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.Abstract:
Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.read more
Citations
More filters
Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits
TL;DR: The study found that when detailed implementation issues are taken into account, the actual achievable area savings can be significant less than the previous estimations—the CMS architecture investigated in this study is only about 10% more area efficient than a comparable conventional and widely studied FPGA architecture for implementing datapath circuits.
Journal ArticleDOI
A consistent design methodology for wireless embedded systems
TL;DR: In this paper, the authors present requirements for such tools and show how an open design environment offers a solution to integrate existing EDA tools, allowing for a consistent design flow, considerably speeding up design times.
Book
Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
TL;DR: Language-driven Exploration and Implementation of Partially Re-configurable ASIPs addresses an important segment of the ESL area by modeling partially re- configurationurable processors via high-level Architecture Description Language (ADL).
Journal ArticleDOI
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems
TL;DR: A circuit-level implementation of the data paths in static and dynamic design styles is presented to explore the various performance-power tradeoffs involved and shows that the FPPE provides two orders of magnitude higher throughput.
Proceedings ArticleDOI
Two-level microprocessor-accelerator partitioning
TL;DR: A novel optimal dynamic programming algorithm has what is effectively quadratic runtime complexity, running in just a few seconds for examples with up to 25 accelerators, obtaining an average performance improvement of 35% compared to a traditional single-level bus architecture.
References
More filters
Book
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Bruce Schneier,Phil Sutherland +1 more
TL;DR: This document describes the construction of protocols and their use in the real world, as well as some examples of protocols used in the virtual world.
Proceedings ArticleDOI
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Journal ArticleDOI
Processor reconfiguration through instruction-set metamorphosis
TL;DR: The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described.
Related Papers (5)
A high-performance microarchitecture with hardware-programmable functional units
Rahul Razdan,Michael D. Smith +1 more