Journal ArticleDOI
A physically based mobility model for numerical simulation of nonplanar devices
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TLDR
A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.Abstract:
A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >read more
Citations
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Book ChapterDOI
Uniaxial s-Si Technology
TL;DR: This chapter gives the review of biaxial s-Si technology, which is perceived to be the alternate for the conventional MOS technology at the nanoscale.
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Numerical modeling of highly sensitive resonant detection of THz radiation using a multichannel dispersive plasmonic HEMT
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Proceedings ArticleDOI
Performance comparison of GS-DG-FinFET with impact of high-K in various device Engineering
TL;DR: In this article, the authors compared DG-FinFET and GS-DG-finFET with spacers configuration for sub-threshold slope (SS), threshold voltage roll-off, drain-induced barrier lowering (DIBL), switching current ratio (ION/IOFF ratio) and electrostatic potential.
LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation
TL;DR: In this paper, the authors investigated the benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors using Sentaurus TCAD simulation software.
Proceedings Article
Scaling issues in nanoscale double gate FinFETs with source/drain underlap
Tapas Dutta,Sudeb Dasgupta +1 more
TL;DR: In this paper, various scaling issues related to underlap FinFET devices with channel lengths of 30 nm and fin widths of 10 nm have been investigated in detail through device simulations using the Sentaurus TCAD simulation package.
References
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Book
Analysis and simulation of semiconductor devices
TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
Journal ArticleDOI
A review of some charge transport properties of silicon
TL;DR: In this article, the present knowledge of charge transport properties in silicon, with special emphasis on their application in the design of solid-state devices, is reviewed, and most attention is devoted to experimental findings in the temperature range around 300 K and to high-field properties.
Journal ArticleDOI
Self-Consistent Results for n -Type Si Inversion Layers
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Journal ArticleDOI
Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon
Guido Masetti,M. Severi,S. Solmi +2 more
TL;DR: In this article, the electron mobility data for both arsenic-and boron-doped silicon are presented in the high doping range, and it is shown that electron mobility is significantly lower in As-and Boron-Doped silicon for carrier concentrations higher than 1019cm-3.
Journal ArticleDOI
Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces
S.C. Sun,James D. Plummer +1 more
TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
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