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Journal ArticleDOI

A physically based mobility model for numerical simulation of nonplanar devices

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TLDR
A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.
Abstract
A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

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Citations
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Journal ArticleDOI

Low Field Electron Mobility Degradation in Silicon MOS Transistors Under Uniform Hot Electron Injection

TL;DR: In this article, the mobility degradation of Coulomb scattering with stress induced charged states at the silicon/insulator interface and in the insulator bulk is investigated and interpreted on the basis of a numerical model.
Proceedings ArticleDOI

Simulation of hot-carrier degradation using self-consistent solution of semiconductor energy-balance equations and oxide carrier transport equations

TL;DR: The Si-SiO/sub 2/interface has been modelled as an abrupt heterojunction to simulate hot-carrier injection and transport in oxides of n- and p-channel MOSFETs as discussed by the authors.
Journal ArticleDOI

Investigation on the non-linear behaviour of silicon nanowires and assessment of the biosensing potential

TL;DR: In this article , the conduction characteristics of long, low-doped and relatively thick p-type silicon nanowire (SiNW) with different bias polarities/strengths were investigated to find out the origin of the nonlinear electrical characteristics and to find the applicable bias window for ensuring the gate responsive operation as biosensor.
Journal ArticleDOI

Gated silicon nanowire for thermo-electric power generation and temperature sensing

TL;DR: In this article, unbiased gated intrinsic Si nanowires (NWs) were used for thermoelectric power generation and temperature sensing in gate-all-around ICs, and the double gated (DG) structure with 30 nm gate length showed higher sensitivity to the change of temperature.
Journal ArticleDOI

GAN-Based Framework for Unified Estimation of Process-Induced Random Variation in FinFET

- 01 Jan 2022 - 
TL;DR: In this article , a generative adversarial network (GAN) is proposed to estimate the random variations of fabricated transistors with multiple orders of magnitude speedup compared to the conventional TCAD simulation-based estimation.
References
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Book

Analysis and simulation of semiconductor devices

TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
Journal ArticleDOI

A review of some charge transport properties of silicon

TL;DR: In this article, the present knowledge of charge transport properties in silicon, with special emphasis on their application in the design of solid-state devices, is reviewed, and most attention is devoted to experimental findings in the temperature range around 300 K and to high-field properties.
Journal ArticleDOI

Self-Consistent Results for n -Type Si Inversion Layers

Frank Stern
- 15 Jun 1972 - 
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Journal ArticleDOI

Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon

TL;DR: In this article, the electron mobility data for both arsenic-and boron-doped silicon are presented in the high doping range, and it is shown that electron mobility is significantly lower in As-and Boron-Doped silicon for carrier concentrations higher than 1019cm-3.
Journal ArticleDOI

Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces

TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
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