Journal ArticleDOI
A physically based mobility model for numerical simulation of nonplanar devices
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TLDR
A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.Abstract:
A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >read more
Citations
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Journal ArticleDOI
Performance enhancement of field effect transistor without doping junctions using In0.3Ga0.7As/GaAs for analog/RF applications
TL;DR: In this article, an effective way to increase the performance of the junctionless silicon (JL-Si) transistor for analog/radio frequency (RF) applications is proposed. But the method is limited to the case where the transistors are made of a single-input single-output (SIMO) block.
Journal ArticleDOI
Double-Epilayer Structure for Low Drain Voltage Rating n-Channel Power Trench MOSFET Devices
TL;DR: In this article, double-epilayer structures were studied for n-channel lowvoltage power trench MOSFET devices with drain-to-source voltage (Vds) of 20 V, and various device performance improvements have been observed.
Journal ArticleDOI
Impact of Channel, Stress-Relaxed Buffer, and S/D Si 1−x Ge x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering
TL;DR: In this paper, the effects of channel stress, stress-relaxed buffer (SRB), and source/drain (S/D) epitaxial stress on different bases of FinFET, specifically silicon germanium (SiGe) and Ge-based, were investigated by manipulating the Ge mole fraction inside the three layers.
Proceedings ArticleDOI
Detailed evaluation of different inversion layer electron and hole mobility models
TL;DR: In this article, a comparative and detailed examination of the various inversion layer and bulk mobility models that reside in popular device simulators is presented, in which the maximum percentage difference and the rms error value between the experimental and simulated drain current have been used as the comparison criteria.
Proceedings ArticleDOI
Realistic device simulation in three dimensions (EPROM cell)
TL;DR: The simulation of a realistic floating-gate EPROM (electrically programmable ROM) cell is carried out by the three-dimensional device simulator HFIELDS 3-D in good agreement with measurements, because of the accurate description of both the device geometry and the impurity profile.
References
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Book
Analysis and simulation of semiconductor devices
TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
Journal ArticleDOI
A review of some charge transport properties of silicon
TL;DR: In this article, the present knowledge of charge transport properties in silicon, with special emphasis on their application in the design of solid-state devices, is reviewed, and most attention is devoted to experimental findings in the temperature range around 300 K and to high-field properties.
Journal ArticleDOI
Self-Consistent Results for n -Type Si Inversion Layers
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Journal ArticleDOI
Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon
Guido Masetti,M. Severi,S. Solmi +2 more
TL;DR: In this article, the electron mobility data for both arsenic-and boron-doped silicon are presented in the high doping range, and it is shown that electron mobility is significantly lower in As-and Boron-Doped silicon for carrier concentrations higher than 1019cm-3.
Journal ArticleDOI
Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces
S.C. Sun,James D. Plummer +1 more
TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
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