Journal ArticleDOI
A physically based mobility model for numerical simulation of nonplanar devices
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TLDR
A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.Abstract:
A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >read more
Citations
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Journal ArticleDOI
A Low-Frequency Noise Model for Four-Gate Field-Effect Transistors
J. A. Jiménez Tejada,Abraham Luque Rodriguez,Andres Godoy,Juan Antonio López Villanueva,Francisco M. Gómez-Campos,Salvador Rodríguez-Bolívar +5 more
TL;DR: In this article, a model for low-frequency noise in four-gate FETs (G4-FETs) is presented, which combines volume and surface noise sources.
Journal ArticleDOI
Investigation and analysis of dual-k spacer with different materials and spacer lengths for nanowire-FET performance
TL;DR: In this article, dual-k spacer structures are investigated using a variety of materials along the high k spacer length in detail, and it is shown that not only the higher permittivity materials of high-K spacer boost the on-current but also lower permittivities materials of low-K Spacer effectively reduce the off-current.
Journal ArticleDOI
Closed-Form Analytical Expression for the Conductive and Dissipative Parameters of the MOS-C Equivalent Circuit
TL;DR: In this paper, the overall conductance of a metal-oxide-semiconductor structure, biased in the inversion regime, is described as the superposition of terms depending either on the minority carrier conductance GN or on the interface state dissipative contribution Rit.
Proceedings ArticleDOI
Semi-empirical local NMOS mobility model for 2-D device simulation incorporating screened minority impurity scattering
TL;DR: In this paper, a new phenomenological yet highly accurate local low-field mobility model that incorporates screened minority impurity scattering and reproduces the generalized mobility curve is presented, which is based on the Born approximation.
Journal ArticleDOI
A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance
TL;DR: In this article, a bottom-spacer ground-plane (BSGP) FinFET structure is proposed to increase the source-channel barrier potential by increasing BS height, which reduces drain-induced barrier lowering (DIBL) and sub-threshold swing (S) by grounding the source and drain electric filed.
References
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Book
Analysis and simulation of semiconductor devices
TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
Journal ArticleDOI
A review of some charge transport properties of silicon
TL;DR: In this article, the present knowledge of charge transport properties in silicon, with special emphasis on their application in the design of solid-state devices, is reviewed, and most attention is devoted to experimental findings in the temperature range around 300 K and to high-field properties.
Journal ArticleDOI
Self-Consistent Results for n -Type Si Inversion Layers
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Journal ArticleDOI
Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon
Guido Masetti,M. Severi,S. Solmi +2 more
TL;DR: In this article, the electron mobility data for both arsenic-and boron-doped silicon are presented in the high doping range, and it is shown that electron mobility is significantly lower in As-and Boron-Doped silicon for carrier concentrations higher than 1019cm-3.
Journal ArticleDOI
Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces
S.C. Sun,James D. Plummer +1 more
TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
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