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Journal ArticleDOI

A physically based mobility model for numerical simulation of nonplanar devices

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TLDR
A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.
Abstract
A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

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Proceedings ArticleDOI

Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation

TL;DR: Advanced 3D TCAD process and device simulations is used to gain physical understanding and to optimize the performance/variability of bulk-FinFETs to investigate SRAM random doping fluctuation RDF.
Proceedings ArticleDOI

Temperature effect on the heavy-ion induced Single-Event Transients propagation on a CMOS Bulk 0.18 µm inverters chain

TL;DR: In this paper, a study by device simulation of the heavy ion induced Single-Event Transients (SET) is realized in the 218-418 K range in order to determine the temperature effect on a CMOS bulk 0.18 mum inverter.
Journal ArticleDOI

Parametric Investigation and Design of Junctionless Nanowire Tunnel Field Effect Transistor

TL;DR: In this article, an integrated design based on Gate-All-Around (GAA) silicon junctionless (JL) vertical profile Nanowire (NW) structure has been proposed for JL-NW-Tunnel-Field Effect Transistor, and a uniform high doping concentration (10−19) has been used to make the device a junctionless structure.

High-Speed, Low-Power and Mid-IR Silicon Photonics Applications

Luca Alloatti
TL;DR: In this paper, the first high-speed silicon-organic hybrid (SOH) modulator was demonstrated by exploiting a highly-nonlinear polymer cladding and a silicon waveguide, which achieved three-wave mixing on the SOH platform.
References
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Book

Analysis and simulation of semiconductor devices

TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
Journal ArticleDOI

A review of some charge transport properties of silicon

TL;DR: In this article, the present knowledge of charge transport properties in silicon, with special emphasis on their application in the design of solid-state devices, is reviewed, and most attention is devoted to experimental findings in the temperature range around 300 K and to high-field properties.
Journal ArticleDOI

Self-Consistent Results for n -Type Si Inversion Layers

Frank Stern
- 15 Jun 1972 - 
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Journal ArticleDOI

Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon

TL;DR: In this article, the electron mobility data for both arsenic-and boron-doped silicon are presented in the high doping range, and it is shown that electron mobility is significantly lower in As-and Boron-Doped silicon for carrier concentrations higher than 1019cm-3.
Journal ArticleDOI

Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces

TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
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