Showing papers on "Field-effect transistor published in 2006"

Light-emitting device

Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Abstract: Field-effect transistors (FETs) based on semi-conductor nanowires could one day replace standard silicon MOSFETs in miniature electronic circuits. MOSFETs, or metal-oxide semiconductor field-effect transistors, are a type of transistor used for high-speed switching and in a computer's integrated circuits. A specially designed nanowire with a germanium shell and silicon core has shown promise as a nanometre-scale field-effect transistor: it has a near-perfect channel for electronic conduction. Now, in transistor configuration, this germanium/silicon nanowire is shown to have properties including high conductance and short switching time delay that are better than state-of-the-art silicon MOSFETs. In a transistor configuration, a new germanium/silicon nanowire has characteristics such as conductance, on-current and switching time delay that are better than those of state-of-the-art silicon metal-oxide-semiconductor field-effect transitors. Semiconducting carbon nanotubes1,2 and nanowires3 are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs)4 owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects1,5. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes1,6 and Ge/Si core/shell nanowires7. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit8. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems3,9,10. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear4. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-κ dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures7 and enhanced gate coupling with high-κ dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS µm-1) and on-current (2.1 mA µm-1) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, τ = CV/I, which represents a key metric for device applications4,11, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.

Field-effect transistor including transparent oxide and light-shielding member, and display utilizing the transistor

Abstract: A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.

Piezoelectric field effect transistor and nanoforce sensor based on a single ZnO nanowire.

Abstract: Utilizing the coupled piezoelectric and semiconducting dual properties of ZnO, we demonstrate a piezoelectric field effect transistor (PE-FET) that is composed of a ZnO nanowire (NW) (or nanobelt) bridging across two Ohmic contacts, in which the source to drain current is controlled by the bending of the NW. A possible mechanism for the PE-FET is suggested to be associated with the carrier trapping effect and the creation of a charge depletion zone under elastic deformatioin. This PE-FET has been applied as a force/pressure sensor for measuring forces in the nanonewton range and even smaller with the use of smaller NWs. An almost linear relationship between the bending force and the conductance was found at small bending regions, demonstrating the principle of nanowire-based nanoforce and nanopressure sensors.

Patterning organic single-crystal transistor arrays.

Abstract: Organic flexible electronics are being developed for computer displays, radio frequency identification tags, sensors and devices that have not been dreamt of yet. Practical applications so far are few, as their electrical performance is poor compared with conventional electronics. In terms of charge carrier mobility, however, field-effect transistors made of organic single crystals have a very high performance. The obstacle to the use of single-crystal devices is that they have to be individually hand-made. The report of a method of fabricating large arrays of high performance transistor devices by direct patterning of single crystals onto clean silicon surfaces or flexible plastics may help to change that. The new method retains the high performance of field-effect transistors even after significant bending. Field-effect transistors made of organic single crystals are ideal for studying the charge transport characteristics of organic semiconductor materials1. Their outstanding device performance2,3,4,5,6,7,8, relative to that of transistors made of organic thin films, makes them also attractive candidates for electronic applications such as active matrix displays and sensor arrays. These applications require minimal cross-talk between neighbouring devices. In the case of thin film systems, simple patterning of the active semiconductor layer9,10 minimizes cross-talk. But when using organic single crystals, the only approach currently available for creating arrays of separate devices is manual selection and placing of individual crystals—a process prohibitive for producing devices at high density and with reasonable throughput. In contrast, inorganic crystals have been grown in extended arrays11,12,13, and efficient and large-area fabrication of silicon crystalline islands with high mobilities for electronic applications has been reported14,15. Here we describe a method for effectively fabricating large arrays of single crystals of a wide range of organic semiconductor materials directly onto transistor source–drain electrodes. We find that film domains of octadecyltriethoxysilane microcontact-printed onto either clean Si/SiO2 surfaces or flexible plastic provide control over the nucleation of vapour-grown organic single crystals. This allows us to fabricate large arrays of high-performance organic single-crystal field-effect transistors with mobilities as high as 2.4 cm2 V-1 s-1 and on/off ratios greater than 107, and devices on flexible substrates that retain their performance after significant bending. These results suggest that our fabrication approach constitutes a promising step that might ultimately allow us to utilize high-performance organic single-crystal field-effect transistors for large-area electronics applications.

Silicon Vertically Integrated Nanowire Field Effect Transistors

Abstract: Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.

Heat Generation and Transport in Nanometer-Scale Transistors

Abstract: As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems

Gate Dielectric Chemical Structure−Organic Field-Effect Transistor Performance Correlations for Electron, Hole, and Ambipolar Organic Semiconductors

Abstract: This study describes a general approach for probing semiconductor−dielectric interfacial chemistry effects on organic field-effect transistor performance parameters using bilayer gate dielectrics. Organic semiconductors exhibiting p-/n-type or ambipolar majority charge transport are grown on six different bilayer dielectric structures consisting of various spin-coated polymers/HMDS on 300 nm SiO2/p+-Si, and are characterized by AFM, SEM, and WAXRD, followed by transistor electrical characterization. In the case of air-sensitive (generally high LUMO energy) n-type semiconductors, dielectric surface modifications induce large variations in the corresponding OTFT performance parameters although the film morphologies and microstructures remain similar. In marked contrast, the device performance of air-stable n-type and p-type semiconductors is not significantly affected by the same dielectric surface modifications. Among the bilayer dielectric structures examined, nonpolar polystyrene coatings on SiO2 having ...

Realization of a silicon nanowire vertical surround-gate field-effect transistor.

Abstract: Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. A variety of technical applications, such as nanowires as parts of sensors, and electronic and photonic devices have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid– solid(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires. The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture. In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a p-n-p structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant. Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip. In order to investigate the influence of the Au/n-Si Schottky contact on the nanowire (current–voltage) I–V characteristics, an array of n-doped nanowires vertically grown on an n-type (111)-oriented substrate was imbedded in a spin-coated SiO2 matrix. After removing the thin SiO2 coverage from the Au tips by a short reactive ion etching, contacts 0.6 mm in size were defined by evaporating aluminum onto the sample, such that approximately 10 nanowires were contacted in parallel. The temperature-dependent measurements (shown in Figure 2) were performed by applying a voltage to the Si substrate, while the Al top contact was held at a constant potential. The measurements reveal a strong rectifying behavior with a thermally activated current possessing an activation energy of 0.6 eV. This can be explained by the Au/n-Si Schottky contact dominating the I–V behavior. The fact that the Schottky contact is forward-biased for negative voltages furthermore proves that, as expected, electrons act as majority charge carries. Figure 1. Schematics of a) a conventional p-channel MOSFET and b) a silicon nanowire vertical surround-gate field-effect transistor.

2,7-Diphenyl[1]benzothieno[3,2-b]benzothiophene, a new organic semiconductor for air-stable organic field-effect transistors with mobilities up to 2.0 cm2 V(-1) s(-1).

Abstract: Vapor-deposited thin films of a newly developed sulfur-containing heteroarene, 2,7-diphenyl[1]benzothieno[3,2-b][1]benzothiophene (DPh-BTBT), were used as an active layer of OFETs, which showed excellent FET characteristics in ambient conditions with mobilities of ∼2.0 cm2 V-1 s-1 and Ion/Ioff of 107.

Vertical high-mobility wrap-gated InAs nanowire transistor

Abstract: In this letter, the authors demonstrate a vertical wrap-gated field-effect transistor based on InAs nanowires [Proc. DRC, 2005, p. 157]. The nanowires have a diameter of 80 nm and are grown using selective epitaxy; a matrix of typically 10 /spl times/ 10 vertically standing wires is used as channel in the transistor. The authors measure current saturation at V/sub ds/=0.15 V (V/sub g/=0 V), and a high mobility, compared to the previous nanowire transistors, is deduced.

Plasma wave detection of terahertz radiation by silicon field effects transistors: Responsivity and noise equivalent power

Abstract: Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120–300nm have been studied as room temperature plasma wave detectors of 0.7THz electromagnetic radiation. In agreement with the plasma wave detection theory, the response was found to depend on the gate length and the gate bias. The obtained values of responsivity (⩽200V∕W) and noise equivalent power (⩾10−10W∕Hz0.5) demonstrate the potential of Si MOSFETs as sensitive detectors of terahertz radiation.

High electron mobility lattice-matched AlInN∕GaN field-effect transistor heterostructures

Abstract: Room temperature electron mobility of 1170cm2∕Vs is obtained in an undoped, lattice-matched, Al0.82In0.18N∕GaN field-effect transistor heterostructure, while keeping a high (2.6±0.3)×1013cm−2 electron gas density intrinsic to the Al0.82In0.18N∕GaN material system. This results in a two-dimensional sheet resistance of 210Ω∕◻. The high mobility of these layers, grown by metal-organic vapor phase epitaxy on sapphire substrate, is obtained thanks to the insertion of an optimized AlN interlayer, reducing the alloy related interface roughness scattering.

High‐Performance Organic Single‐Crystal Transistors on Flexible Substrates

Abstract: The electronic properties of organic single crystals have been intensely studied for well over 40 years. Until recently, organic single-crystal field-effect transistors have generated results that are comparable to and sometimes better in performance than hydrogenated amorphous silicon. Organic thin-film transistors are being actively pursued for a broad area of electronic applications, but their charge-carrier mobilities are limited by structural imperfections (i.e., grain boundaries) and impurities. Organic single crystals, on the other hand, have been limited to charge-transport studies mainly because the fabrication of single-crystal transistors poses a technological challenge. Novel methods for fabricating single-crystal devices include the flip-crystal technique, elastomeric stamp platforms, and freestanding devices, where the source–drain electrodes, dielectric, and gate are all fabricated onto the crystal surface. For the most part, a relatively thick and rigid single crystal is employed (5–500 lm thick). Because the fragility makes them difficult to handle, their use has been restricted to simple and basic devices and wide-ranging applications in sensors or plastic transistors for flexible electronics have not yet been possible. Thus, there is a strong need for the development of mechanically flexible, nondestructive, single-crystal devices with prospective applications in organic electronics while maintaining the intrinsic properties and characteristics of organic single crystals. We demonstrate field-effect transistors fabricated from thin and conformable organic single crystals. We report on proofof-concept “flexible” organic single-crystal field-effect transistors with performance exceeding those of previously reported organic thin-film flexible devices. Rubrene single-crystal devices constructed on low-cost flexible substrates (Fig. 1b) yielded mobilities as high as 4.6 cm V s and on/off ratios of approximately 10.

Organic Non-Volatile Memory Based on Pentacene Field-Effect Transistors Using a Polymeric Gate Electret**

Abstract: electrets. In this Communication, we report on OFET memory devices built on silicon wafers and based on films of pentacene and an SiO2 gate insulator that are separated by a thin layer of poly(a-methylstyrene) (PaMS), which acts as a polymeric gate dielectric. This OFET memory device displayed reversible shifts in the threshold voltage (VTh) when an appropriate gate voltage (Vg) was applied above a certain threshold via a relatively short switching time. Based on these reversible shifts in VTh, a non-volatile organic memory was demonstrated that takes advantage of the simple configuration of a typical OFET. This device showed a large memory window (about 90 V), a high on/off ratio (IOn/IOff) (10 5 ), a short switching time (less than 1 ls), and a long retention time (more than 100 h). These memory characteristics were obtained only when an appropriate polymeric gate electret layer (e.g., PaMS) was inserted between the SiO2 gate insulator and the pentacene channel in the typical OFET structure. Therefore, it is possible that this behavior originates from the modulation of the gate field by stored charges in the polymeric gate electret. Detailed reasons for these results and a possible operating mechanism for our OFET memory device are discussed. A cross-sectional view of the fabricated device structure is shown in Figure 1a. Further details concerning the fabrication of this device are discussed in the Experimental section. Figure 1b and c shows the output and transfer characteristics of the devices, respectively. The results indicate reasonably good OFET behavior, suggesting the additional PaMS layer does not degrade the performance of the devices. [14] From the conventional characterization equation, [15] the measured values of the typical field-effect mobility (lFET), VTh, and IOn/IOff were 0.51 cm 2 V –1 s –1 (maximum value, 0.89 cm 2 V –1 s –1 ), – 19 V, and 10 5 , respectively. These transistor properties could

Germanium-source tunnel field effect transistors with record high I ON /I OFF

Abstract: Tunnel field effect transistors (TFETs) with record high I ON /I OFF ratio (≫106) for low-voltage (0.5V) operation are achieved by using germanium in the source region to achieve a small tunnel bandgap. The measured data are well explained by the theoretical band-to-band tunneling current model. Using the calibrated analytical model, the energy-delay performance of TFET-based technology is compared against that of conventional CMOS technology, at the 65nm node. The TFET is projected to provide dramatic improvement in energy efficiency for performance in the range up to ∼0.5GHz.

Network single-walled carbon nanotube-field effect transistors (SWNT-FETs) with increased Schottky contact area for highly sensitive biosensor applications.

Abstract: Highly sensitive single-walled carbon nanotube-field effect transistor (SWNT-FET) devices, which detect protein adsorptions and specific protein−protein interactions at 1 pM concentrations, have been achieved. The detection limit has been improved 104-fold compared to the devices fabricated by photolithography. The substantially increased sensitivity is mainly due to the increased Schottky contact area which accommodates relatively more numbers of proteins even at very low concentration. The augmented number of proteins adsorbed on a device induces instant modulation of the work function of metal contact electrodes, which eventually changes the conductance of the device. Such devices have been attained by addressing metal electrodes on network-type SWNTs using a shadow mask on a tilted angle sample stage. The shadow mask allows metals to penetrate underneath the mask efficiently, therefore forming a thin and wide Schottky contact area on SWNT channels.

Semiconductor device and a method of manufacturing the same

Abstract: To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This relatively lessens a stress generated in an active region ACT sandwiched by the element isolation regions even if the isolation width of each element isolation region is made relatively small, specifically, less than 0.3 mum. It is therefore possible to relax or prevent the generation of crystal defects resulting from the stress, thereby reducing occurrence of an undesired leak current between the source and drain of each field effect transistor.

Gate capacitance of back-gated nanowire field-effect transistors

Abstract: Gate capacitances of back-gated nanowire field-effect transistors (NW-FETs) are calculated by means of finite element methods and the results are compared with analytical results of the “metallic cylinder on an infinite metal plate model.” Completely embedded and nonembedded NW-FETs are considered. It is shown that the use of the analytical expressions also for nonembedded NW-FETs gives carrier mobilities that are nearly two times too small. Furthermore, the electric field amplification of nonembedded NW-FETs and the influence of the cross section shape of the nanowires are discussed.

High performance n-channel organic field-effect transistors and ring oscillators based on C60 fullerene films

Abstract: We report on organic n-channel field-effect transistors and circuits based on C60 films grown by hot wall epitaxy. Electron mobility is found to be dependent strongly on the substrate temperature during film growth and on the type of the gate dielectric employed. Top-contact transistors employing LiF∕Al electrodes and a polymer dielectric exhibit maximum electron mobility of 6cm2∕Vs. When the same films are employed in bottom-contact transistors, using SiO2 as gate dielectric, mobility is reduced to 0.2cm2∕Vs. By integrating several transistors we are able to fabricate high performance unipolar (n-channel) ring oscillators with stage delay of 2.3μs.

Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions

Abstract: High- κ gate dielectrics like HfO 2 and HfSiO(N) are considered for the replacement of SiO 2 and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices. Using these gate oxides allows indeed to drastically reduce the leakage current flowing through the device, as required by the specifications of the International Technology Roadmap for Semiconductors. However, major problems remain to be solved before the possible use of high- κ gate dielectrics in integrated circuits. The purpose of this paper is to give an overview of the challenges and issues pertaining to high- κ -based devices. Several issues are discussed in detail, like flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate dielectric wear-out and breakdown, and bias temperature instabilities. Our current understanding of these issues is presented, with an emphasis on the relationship between the material properties of the gate stack, and the electrical properties of the devices. The combination of metal gates with high- κ gate dielectric appears to be a promising solution for the further scaling down of CMOS devices.

High-performance ZnO nanowire field effect transistors

Abstract: ZnO nanowires with high crystalline and optical properties are characterized, showing strong effect of the surface defect states. In order to optimize the performance of devices based on these nanowires, a series of complementary metal-oxide semiconductor compatible surface passivation procedures is employed. Electrical transport measurements demonstrate significantly reduced subthreshold swing, high on/off ratio, and unprecedented field effect mobility.

Silicon-Nanowire Transistors with Intruded Nickel-Silicide Contacts

Abstract: Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths. The gate length was shortened by the axial, self-aligned formation of nickel-silicide source and drain segments along the NW. The transistors with 10−30 nm NW diameters displayed p-type behaviour, sustained current densities of up to 0.5 MA/cm2, and exhibited on/off current ratios of up to 107. The on-currents were limited and kept constant by the Schottky contacts for gate lengths below 1 μm, and decreased exponentially for gate lengths exceeding 1 μm.

Anisotropic field effect mobility in single crystal pentacene

Abstract: Fan-shaped electrodes were designed on Si∕SiO2 substrate to measure the anisotropic field effect mobility in freestanding single crystal pentacene. Field effect transistor was fabricated by placing single crystal pentacene on the prepatterned electrodes. The contact between the electrodes and single crystal pentacene was enhanced by applying pressure. Angle dependence of field effect mobility in single crystal pentacene showed remarkably anisotropic behavior. The highest mobility value was estimated to be ∼2.3cm2∕Vs at room temperature.

Air-Stable Complementary-like Circuits Based on Organic Ambipolar Transistors†

Abstract: To date there are two demonstrated technologies for the fabrication of organic integrated circuits: the unipolar and the complementary technology. Unipolar architectures consist of p-channel organic field-effect transistors (OFETs), which are simple to fabricate since they require a single, high-workfunction metal (e.g., gold) and a single semiconductor material, which can be either evaporated or solution-processed.[1–4] Despite this great advantage, unipolar circuits have poor performance, exhibiting a narrow noise margin, low yield, and high power consumption.[2] In order to improve their performance, more sophisticated architectures are usually employed.[5] Although beneficial, such an approach increases circuit complexity by nearly 100 %. Complementary architectures, adopted from silicon microelectronics, solve this bottleneck by providing major advantages in circuit performance, including wide noise margin, robustness, and low power dissipation.[6,7] Unlike silicon technology, however, fabrication of discrete organic n- and p-channel transistors with lateral dimensions of a few micrometers, typically required for largescale integration, is still very challenging.

Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film

Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.

Integrated circuit and method for its manufacture

Abstract: An integrated circuit and methods for its manufacture are provided. The integrated circuit (20) comprises a bulk silicon substrate (24) having a first region (64, 66) of (100) crystalline orientation and a second region (66, 64) of (110) crystalline orientation. A layer (62) of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor (96, 98) is formed in the layer (62) of silicon on insulator, at least one P-channel field effect transistor (90, 92) is formed in the second region (66, 64) of (110) crystalline orientation, and at least one N-channel field effect transistor (90, 92) is formed in the first region (64, 66) of (100) crystalline orientation.

Flexible ferroelectret field-effect transistor for large-area sensor skins and microphones

Abstract: Ferroelectrets generate an electric field large enough to modulate the conductance of the source-drain channel of a thin-film field-effect transistor. Integrating a ferroelectret with a thin-film transistor produces a ferroelectret field-effect transistor. The authors made such transistors by laminating cellular polypropylene films and amorphous silicon thin-film transistors on polyimide substrates. They show that these ferrroelectret field-effect transistors respond in a static capacitive or dynamic piezoelectric mode. A touch sensor, a pressure-activated switch, and a microphone are demonstrated. The structure can be scaled up to large-area flexible transducer arrays, such as roll-up steerable compliant sensor skin.

2,6-Bis[2-(4-pentylphenyl)vinyl]anthracene: a stable and high charge mobility organic semiconductor with densely packed crystal structure.

Abstract: The development of new organic semiconductors with improved electrical performance and enhanced environmental stability is the focus of considerable research activity. This paper presents the design, synthesis, optical and electrochemical characterization, crystal packing, modeling and thin film morphology, and organic thin film field effect transistor (OTFT) device data analysis for a novel 2,6-bis[2-(4-pentylphenyl)vinyl]anthracene (DPPVAnt) organic semiconductor. We observed a hole mobility of up to 1.28 cm2/V.s and on/off current ratios greater than 107 for OTFTs fabricated using DPPVAnt as an active semiconductor layer. The mobility value is comparable to that of the current best p-type semiconductor pentacene-based device performance. In addition, we found a very interesting relationship between the charge mobility and molecule crystal packing in addition to the thin film orientation and morphology of the semiconductor as determined from single-crystal molecule packing study, thin film X-ray diffraction, and AFM measurements. The high performance of the semiconductor ranks among the best performing p-type organic semiconductors reported so far and will be a very good candidate for applications in organic electronic devices.