Showing papers on "Field-effect transistor published in 2019"

A ferroelectric semiconductor field-effect transistor

Abstract: Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are potentially of use in non-volatile memory technology, but they suffer from short retention times, which limits their wider application. Here, we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, room-temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers and its potential for large-area growth. A passivation method based on the atomic layer deposition of aluminium oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on current of 862 μA μm−1 and a low supply voltage. A ferroelectric semiconductor field-effect transistor, which uses the two-dimensional ferroelectric semiconductor α-In2Se3 as a channel material, could offer enhanced capabilities compared with conventional ferroelectric field-effect transistors in non-volatile memory applications.

Spin tunnel field-effect transistors based on two-dimensional van der Waals heterostructures

Abstract: A transistor based on spin rather than charge—a spin transistor—could potentially offer non-volatile data storage and improved performance compared with traditional transistors. Many approaches have been explored to realize spin transistors, but their development remains a considerable challenge. The recent discovery of two-dimensional magnetic insulators such as chromium triiodide (CrI3), which offer electrically switchable magnetic order and an effective spin filtering effect, can provide new operating principles for spin transistors. Here, we report spin tunnel field-effect transistors (TFETs) based on dual-gated graphene/CrI3/graphene tunnel junctions. The devices exhibit an ambipolar behaviour and tunnel conductance that is dependent on the magnetic order in the CrI3 tunnel barrier. The gate voltage switches the tunnel barrier between interlayer antiferromagnetic and ferromagnetic states under a constant magnetic bias near the spin-flip transition, thus effectively and reversibly altering the device between a low and a high conductance state, with large hysteresis. By electrically controlling the magnetization configurations instead of the spin current, our spin TFETs achieve a high–low conductance ratio approaching 400%, suggesting they could be of value in the development of non-volatile memory applications. A tunnel field-effect transistor with spin-dependent outputs that are voltage controllable and reversible can be created using a dual-gated graphene/CrI3/graphene tunnel junction.

Lowering the Schottky Barrier Height by Graphene/Ag Electrodes for High‐Mobility MoS2 Field‐Effect Transistors

Abstract: 2D transition metal dichalcogenides (TMDCs) have emerged as promising candidates for post-silicon nanoelectronics owing to their unique and outstanding semiconducting properties. However, contact engineering for these materials to create high-performance devices while adapting for large-area fabrication is still in its nascent stages. In this study, graphene/Ag contacts are introduced into MoS2 devices, for which a graphene film synthesized by chemical vapor deposition (CVD) is inserted between a CVD-grown MoS2 film and a Ag electrode as an interfacial layer. The MoS2 field-effect transistors with graphene/Ag contacts show improved electrical and photoelectrical properties, achieving a field-effect mobility of 35 cm2 V-1 s-1 , an on/off current ratio of 4 × 108 , and a photoresponsivity of 2160 A W-1 , compared to those of devices with conventional Ti/Au contacts. These improvements are attributed to the low work function of Ag and the tunability of graphene Fermi level; the n-doping of Ag in graphene decreases its Fermi level, thereby reducing the Schottky barrier height and contact resistance between the MoS2 and electrodes. This demonstration of contact interface engineering with CVD-grown MoS2 and graphene is a key step toward the practical application of atomically thin TMDC-based devices with low-resistance contacts for high-performance large-area electronics and optoelectronics.

Ultrathin calcium fluoride insulators for two-dimensional field-effect transistors

Abstract: Two-dimensional semiconductors could be used to fabricate ultimately scaled field-effect transistors and more-than-Moore nanoelectronic devices. However, these targets cannot be reached without appropriate gate insulators that are scalable to the nanometre range. Typically used oxides such as SiO2, Al2O3 and HfO2 are, however, amorphous when scaled, and 2D hexagonal boron nitride exhibits excessive gate leakage currents. Here, we show that epitaxial calcium fluoride (CaF2), which can form a quasi van der Waals interface with 2D semiconductors, can serve as an ultrathin gate insulator for 2D devices. We fabricate scalable bilayer MoS2 field-effect transistors with a crystalline CaF2 insulator of ~2 nm thickness, which corresponds to an equivalent oxide thickness of less than 1 nm. Our devices exhibit low leakage currents and competitive device performance characteristics, including subthreshold swings down to 90 mV dec−1, on/off current ratios up to 107 and a small hysteresis. High-performance MoS2 transistors can be created using 2-nm-thick CaF2 as a gate insulator, which forms a quasi van der Waals interface with the 2D semiconductor.

$\beta$ -Ga 2 O 3 Delta-Doped Field-Effect Transistors With Current Gain Cutoff Frequency of 27 GHz

Abstract: As an ultra-wide bandgap semiconductor, $\beta $ -Ga2O3 has attracted great attention for high-power, high-voltage, and optoelectronic applications. However, until now, high-frequency performance of gallium oxide devices has been limited to relatively low current gain cutoff frequencies below 5 GHz. Here, we show that highly localized delta-doping designs can enable high-sheet-charge density to enable devices with short gate lengths that allow high-frequency operation. Field-effect transistors with a gate length of 120 nm on such delta-doped $\beta $ -Ga2O3 are reported here with extrinsic unity current gain frequency of 27 GHz. The device has a peak drain current of 260 mA/mm, transconductance (gm) of 44 mS/mm, and three-terminal off-state breakdown voltage of 150 V. These results demonstrate that the potential of $\beta $ -Ga2O3 for future RF and millimeter-wave device applications.

A critical review of recent progress on negative capacitance field-effect transistors

Abstract: The elegant simplicity of the device concept and the urgent need for a new "transistor" at the twilight of Moore's law have inspired many researchers in industry and academia to explore the physics and technology of negative capacitance field effect transistor (NC-FET). Although hundreds of papers have been published, the validity of quasi-static NC and the frequency-reliability limits of NC-FET are still being debated. The concept of NC - if conclusively demonstrated - will have broad impacts on device physics and technology development. Here, the authors provide a critical review of recent progress on NC-FETs research and some starting points for a coherent discussion.

A Critical Review of Recent Progress on Negative Capacitance Field-Effect Transistors.

Abstract: The elegant simplicity of the device concept and the urgent need for a new "transistor" at the twilight of Moore's law have inspired many researchers in industry and academia to explore the physics and technology of negative capacitance field effect transistor (NC-FET). Although hundreds of papers have been published, the validity of quasi-static NC and the frequency-reliability limits of NC-FET are still being debated. The concept of NC - if conclusively demonstrated - will have broad impacts on device physics and technology development. Here, the authors provide a critical review of recent progress on NC-FETs research and some starting points for a coherent discussion.

Strain-Based Room-Temperature Non-Volatile MoTe$_2$ Ferroelectric Phase Change Transistor

Abstract: The primary mechanism of operation of almost all transistors today relies on electric-field effect in a semiconducting channel to tune its conductivity from the conducting 'on'-state to a non-conducting 'off'-state. As transistors continue to scale down to increase computational performance, physical limitations from nanoscale field-effect operation begin to cause undesirable current leakage that is detrimental to the continued advancement of computing. Using a fundamentally different mechanism of operation, we show that through nanoscale strain engineering with thin films and ferroelectrics (FEs) the transition metal dichalcogenide (TMDC) MoTe$_2$ can be reversibly switched with electric-field induced strain between the 1T'-MoTe$_2$ (semimetallic) phase to a semiconducting MoTe$_2$ phase in a field effect transistor geometry. This alternative mechanism for transistor switching sidesteps all the static and dynamic power consumption problems in conventional field-effect transistors (FETs). Using strain, we achieve large non-volatile changes in channel conductivity (G$_{on}$/G$_{off}$~10$^7$ vs. G$_{on}$/G$_{off}$~0.04 in the control device) at room temperature. Ferroelectric devices offer the potential to reach sub-ns nonvolatile strain switching at the attojoule/bit level, having immediate applications in ultra-fast low-power non-volatile logic and memory while also transforming the landscape of computational architectures since conventional power, speed, and volatility considerations for microelectronics may no longer exist.

Low Residual Carrier Concentration and High Mobility in 2D Semiconducting Bi2O2Se.

Abstract: The air-stable and high-mobility two-dimensional (2D) Bi2O2Se semiconductor has emerged as a promising alternative that is complementary to graphene, MoS2, and black phosphorus for next-generation digital applications. However, the room-temperature residual charge carrier concentration of 2D Bi2O2Se nanoplates synthesized so far is as high as about 1019–1020 cm–3, which results in a poor electrostatic gate control and unsuitable threshold voltage, detrimental to the fabrication of high-performance low-power devices. Here, we first present a facile approach for synthesizing 2D Bi2O2Se single crystals with ultralow carrier concentration of ∼1016 cm–3 and high Hall mobility up to 410 cm2 V–1 s–1 simultaneously at room temperature. With optimized conditions, these high-mobility and low-carrier-concentration 2D Bi2O2Se nanoplates with domain sizes greater than 250 μm and thicknesses down to 4 layers (∼2.5 nm) were readily grown by using Se and Bi2O3 powders as coevaporation sources in a dual heating zone chemi...

Pressure-Tunable Ambipolar Conduction and Hysteresis in Ultrathin Palladium Diselenide Field Effect Transistors

Abstract: A few-layer palladium diselenide (PdSe2) field effect transistor is studied under external stimuli such as electrical and optical fields, electron irradiation and gas pressure. We observe ambipolar conduction and hysteresis in the transfer curves of the PdSe2 material unprotected and as-exfoliated. We tune the ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments. The prevailing p-type transport observed at room pressure is reversibly turned into dominant n-type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The pressure control can be exploited to symmetrize and stabilize the transfer characteristic of the device as required in high-performance logic circuits. The transistor is immune from short channel effects but is affected by trap states with characteristic times in the order of minutes. The channel conductance, dramatically reduced by the electron irradiation during scanning electron microscope imaging, is restored after several minutes anneal at room temperature. The work paves the way toward the exploitation of PdSe2 in electronic devices by providing an experiment-based and deeper understanding of charge transport in PdSe2 transistors subjected to electrical stress and other external agents.

Shallow and Undoped Germanium Quantum Wells: A Playground for Spin and Hybrid Quantum Technology

Abstract: Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 105 cm2 V−1 s−1) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 1011cm−2, light effective mass (0.09me), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.

Device-Level Thermal Management of Gallium Oxide Field-Effect Transistors

Abstract: The ultrawide bandgap (UWBG) (~4.8 eV) and melt-grown substrate availability of $\beta $ -Ga2O3 give promise to the development of next-generation power electronic devices with dramatically improved size, weight, power, and efficiency over current state-of-the-art WBG devices based on 4H-SiC and GaN. Also, with recent advancements made in gigahertz frequency radio frequency (RF) applications, the potential for monolithic or heterogenous integration of RF and power switches has attracted researchers’ attention. However, it is expected that Ga2O3 devices will suffer from self-heating due to the poor thermal conductivity of the material. Thermoreflectance thermal imaging and infrared thermography were used to understand the thermal characteristics of a MOSFET fabricated via homoepitaxy. A 3-D coupled electrothermal model was constructed based on the electrical and thermal characterization results. The device model shows that a homoepitaxial device suffers from an unacceptable junction temperature rise of ~1500 °C under a targeted power density of 10 W/mm, indicating the importance of employing device-level thermal managements to individual Ga2O3 transistors. The effectiveness of various active and passive cooling solutions was tested to achieve a goal of reducing the device operating temperature below 200 °C at a power density of 10 W/mm. Results show that flip-chip heterointegration is a viable option to enhance both the steady-state and transient thermal characteristics of Ga2O3 devices without sacrificing the intrinsic advantage of high-quality native substrates. Also, it is not an active thermal management solution that entails peripherals requiring additional size and cost implications.

Gas dependent hysteresis in MoS 2 field effect transistors

Abstract: We study the effect of electric stress, gas pressure and gas type on the hysteresis in the transfer characteristics of monolayer molybdenum disulfide (MoS2) field effect transistors. The presence of defects and point vacancies in the MoS2 crystal structure facilitates the adsorption of oxygen, nitrogen, hydrogen or methane, which strongly affect the transistor electrical characteristics. Although the gas adsorption does not modify the conduction type, we demonstrate a correlation between hysteresis width and adsorption energy onto the MoS2 surface. We show that hysteresis is controllable by pressure and/or gas type. Hysteresis features two well-separated current levels, especially when gases are stably adsorbed on the channel, which can be exploited in memory devices. PAPER 2019

Bulk and few-layer MnPS3: a new candidate for field effect transistors and UV photodetectors

Abstract: Layered metal thiophosphates with the general formula MPX3 (M is a group VI element and X is a chalcogen) have been emerging as a novel group of tunable bandgap semiconductors. Herein, we report the synthesis of high quality MnPS3 crystals, and their mechanical exfoliation onto pre-fabricated devices. The use of atomic force microscopy and Raman spectroscopy yielded information on the number of layers. MnPS3-based field effect transistors (FETs) comprising few-layer and bulk crystals with gold contacts show p-type conductivity with an on–off ratio of ∼103. Temperature dependent electrical transport measurements yield a Schottky barrier height value of 0.34 eV for few-layer devices. FETs based on multilayer and bulk MnPS3 show very similar transport characteristics. The transistor devices have also been shown to be good ultraviolet photodetectors with photoresponsivity of 288 A W−1 at a wavelength of 365 nm. Density functional theory calculations reveal the parameters that affect the viability of electron/hole doping in MnPS3 and help understand the p-type nature of the FET device.

Investigation of Electrode Electrochemical Reactions in CH 3 NH 3 PbBr 3 Perovskite Single-Crystal Field-Effect Transistors

Abstract: Optoelectronic devices based on metal halide perovskites, including solar cells and light-emitting diodes, have attracted tremendous research attention globally in the last decade. Due to their potential to achieve high carrier mobilities, organic-inorganic hybrid perovskite materials can enable high-performance, solution-processed field-effect transistors (FETs) for next-generation, low-cost, flexible electronic circuits and displays. However, the performance of perovskite FETs is hampered predominantly by device instabilities, whose origin remains poorly understood. Here, perovskite single-crystal FETs based on methylammonium lead bromide are studied and device instabilities due to electrochemical reactions at the interface between the perovskite and gold source-drain top contacts are investigated. Despite forming the contacts by a gentle, soft lamination method, evidence is found that even at such "ideal" interfaces, a defective, intermixed layer is formed at the interface upon biasing of the device. Using a bottom-contact, bottom-gate architecture, it is shown that it is possible to minimize such a reaction through a chemical modification of the electrodes, and this enables fabrication of perovskite single-crystal FETs with high mobility of up to ≈15 cm2 V-1 s-1 at 80 K. This work addresses one of the key challenges toward the realization of high-performance solution-processed perovskite FETs.

High-speed black phosphorus field-effect transistors approaching ballistic limit.

Abstract: As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation. By designing the device channels along the lower effective mass armchair direction, a record-high drive current up to 1.2 mA/μm at 300 K and 1.6 mA/μm at 20 K can be achieved in a 100-nm back-gated BP transistor, surpassing any two-dimensional semiconductor transistors reported to date. The highest hole saturation velocity of 1.5 × 107 cm/s is also achieved at room temperature. Ballistic transport shows a record-high 36 and 79% ballistic efficiency at room temperature and 20 K, respectively, which is also further verified by theoretical simulations.

Gate-Controlled Metal-Insulator Transition in TiS 3 Nanowire Field-Effect Transistors

Abstract: We explore the electrical characteristics of TiS3 nanowire field-effect transistor (FETs), over the wide temperature range from 3 to 350 K. These nanomaterials have a quasi-one-dimensional (1D) crystal structure and exhibit a gate-controlled metal-insulator transition (MIT) in their transfer curves. Their room-temperature mobility is ∼20-30 cm2/(V s), 2 orders of magnitude smaller than predicted previously, a result that we explain quantitatively in terms of the influence of polar-optical phonon scattering in these materials. In the insulating state (<∼220 K), the transfer curves exhibit unusual mesoscopic fluctuations and a current suppression near zero bias that is common to charge-density wave (CDW) systems. The fluctuations have a nonmonotonic temperature dependence and wash out at a temperature close to that of the bulk MIT, suggesting they may be a feature of quantum interference in the CDW state. Overall, our results demonstrate that quasi-1D TiS3 nanostructures represent a viable candidate for FET realization and that their functionality is influenced by complex phenomena.

Effect of Electron Irradiation on the Transport and Field Emission Properties of Few-Layer MoS2 Field-Effect Transistors

Abstract: Electrical characterization of few-layer MoS2-based field-effect transistors with Ti/Au electrodes is performed in the vacuum chamber of a scanning electron microscope in order to study the effects...

Photonic crystal for graphene plasmons

Abstract: Photonic crystals are commonly implemented in media with periodically varying optical properties. Photonic crystals enable exquisite control of light propagation in integrated optical circuits, and also emulate advanced physical concepts. However, common photonic crystals are unfit for in-operando on/off controls. We overcome this limitation and demonstrate a broadly tunable two-dimensional photonic crystal for surface plasmon polaritons. Our platform consists of a continuous graphene monolayer integrated in a back-gated platform with nano-structured gate insulators. Infrared nano-imaging reveals the formation of a photonic bandgap and strong modulation of the local plasmonic density of states that can be turned on/off or gradually tuned by the applied gate voltage. We also implement an artificial domain wall which supports highly confined one-dimensional plasmonic modes. Our electrostatically-tunable photonic crystals are derived from standard metal oxide semiconductor field effect transistor technology and pave a way for practical on-chip light manipulation.

Magnetotransport Experiments on Fully Metallic Superconducting Dayem-Bridge Field-Effect Transistors

Abstract: The field effect, as in a field-effect transistor (FET), allows control of the switching current in a metallic superconductor, without affecting the critical temperature or normal-state resistance. Here magnetotransport experiments on Ti-based superconducting FETs reveal several physical insights: The phenomenon occurs at the sample surface, the field effect causes a transition from ballistic to tunnel-like behavior, and a mixed superconducting--normal-metal state is possible at high gate voltages. Such a device could be the cornerstone of easily fabricated monolithic architectures for classical or quantum computing, and a host of other applications in (opto)electronics.

Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper

Abstract: Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging from wearable electronics to smart packaging. Here we report high-performance MoS2 field-effect transistors on paper fabricated with a channel-array approach, combining the advantages of two large-area techniques: chemical vapor deposition and inkjet-printing.The first allows the pre-deposition of a pattern of MoS2; the second, the printing of dielectric layers, contacts, and connections to complete transistors and circuits fabrication. Average ION/IOFF of 8 x 10^3 (up to 5 x 10^4) and mobility of 5.5 cm2 V-1 s-1 (up to 26 cm2 V-1 s-1) are obtained. Fully functional integrated circuits of digital and analog building blocks, such as logic gates and current mirrors, are demonstrated, highlighting the potential of this approach for ubiquitous electronics on paper.

High Dielectric Constant Polycarbonate/Nylon Multilayer Films Capacitors with Self-Healing Capability

Abstract: With the fast development of high-temperature metal oxide semiconductor field effect transistors for power electronics in electric vehicles, current state-of-the-art biaxially oriented polypropylen...

Solution-Processed Organic Field-Effect Transistors with High Performance and Stability on Paper Substrates.

Abstract: High-performance operationally stable organic field-effect transistors were successfully fabricated on a PowerCoat HD 230 paper substrate with a TIPS-pentacene:polystyrene blend as the active layer and poly(4-vinylphenol)/HfO2 as the hybrid gate dielectric. The fabricated devices exhibited excellent p-channel characteristics with a maximum and av field effect mobility of 0.44 and 0.22(±0.11) cm2 V–1 s–1, respectively, av threshold voltage of 0.021(±0.63) V, and current on–off ratio of ∼105 while operating at −10 V. These devices exhibited remarkable stability under effects of gate bias stress and large number of repeated transfer scans with negligible performance spread. In addition, these devices displayed very stable electrical characteristics after long exposure periods to humidity and an excellent shelf life of more than 6 months in ambient environment. Thermal stress at high temperatures however deteriorates the device characteristics because of the generation and propagation of cracks in the active ...

A Compact Series-Connected SiC MOSFETs Module and Its Application in High Voltage Nanosecond Pulse Generator

Abstract: Nanosecond pulse discharge plasma has many prospects in industrial applications, and high-voltage repetitive nanosecond pulse generators with compact design and light weight have become one of the key issues limiting its development in some applications. This paper presents a high voltage series-connected silicon carbide (SiC) metal-oxide -semiconductor field effect transistor ( MOSFET s) module which can be served as the main switch in a repetitive high-voltage nanosecond pulse generator. This kind of series-connected MOSFET s module with only single external gate driver requiring very few components is very suitable for compact assembly. By analyzing the working principle, three topologies of series-connected MOSFET s module are proposed. The switching behaviors of the three different topologies with four SiC MOSFET s series-connected are compared experimentally. The variation of switching characteristics of series-connection SiC MOSFET s module with different numbers of devices are investigated. The layout is also optimized to shorten pulse front time and improve output pulse quality. Furthermore, a 10 kV SiC MOSFET s module with a turn- on transition time ∼10 ns is developed. The double pulse test result demonstrates excellent switching performances. Finally, a compact and high-voltage pulse generator composed of three 10 kV SiC MOSFET s module is tailored, with a typical rise time ∼40 ns and peak voltage of ∼30 kV.

A Single Gate Driver Based Solid-State Circuit Breaker Using Series Connected SiC MOSFETs

Abstract: Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfet s), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfet s to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on -state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs.