Showing papers on "Transistor published in 2021"

Strain-insensitive intrinsically stretchable transistors and circuits

Abstract: Intrinsically stretchable electronics can form intimate interfaces with the human body, creating devices that could be used to monitor physiological signals without constraining movement. However, mechanical strain invariably leads to the degradation of the electronic properties of the devices. Here we show that strain-insensitive intrinsically stretchable transistor arrays can be created using an all-elastomer strain engineering approach, in which the patterned elastomer layers with tunable stiffnesses are incorporated into the transistor structure. By varying the cross-linking density of the elastomers, areas of increased local stiffness are introduced, reducing strain on the active regions of the devices. This approach can be readily incorporated into existing fabrication processes, and we use it to create arrays with a device density of 340 transistors cm–2 and a strain insensitivity of less than 5% performance variation when stretched to 100% strain. We also show that it can be used to fabricate strain-insensitive circuit elements, including NOR gates, ring oscillators and high-gain amplifiers for the stable monitoring of electrophysiological signals. An all-elastomer strain engineering approach, which uses patterned elastomer layers with tunable stiffnesses, can be used to create intrinsically stretchable transistor arrays with a device density of 340 transistors cm–2 and strain insensitivity of less than 5% performance variation when stretched to 100% strain.

Monolithic optical microlithography of high-density elastic circuits.

Abstract: Polymeric electronic materials have enabled soft and stretchable electronics. However, the lack of a universal micro/nanofabrication method for skin-like and elastic circuits results in low device density and limited parallel signal recording and processing ability relative to silicon-based devices. We present a monolithic optical microlithographic process that directly micropatterns a set of elastic electronic materials by sequential ultraviolet light-triggered solubility modulation. We fabricated transistors with channel lengths of 2 micrometers at a density of 42,000 transistors per square centimeter. We fabricated elastic circuits including an XOR gate and a half adder, both of which are essential components for an arithmetic logic unit. Our process offers a route to realize wafer-level fabrication of complex, high-density, and multilayered elastic circuits with performance rivaling that of their rigid counterparts.

Gallium nitride-based complementary logic integrated circuits

Abstract: Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. Through the monolithic integration of enhancement-mode n-type and p-type gallium nitride field-effect transistors, complementary integrated circuits including latch circuits and ring oscillators can be created for use in high-power and high-frequency applications.

Two-dimensional transistors with reconfigurable polarities for secure circuits

Abstract: Security is a critical aspect in modern circuit design, but research into hardware security at the device level is rare as it requires modification of existing technology nodes. With the increasing challenges facing the semiconductor industry, interest in out-of-the-box security solutions has grown, even if this implies introducing novel materials such as two-dimensional layered semiconductors. Here, we show that high-performance, low-voltage, two-dimensional black phosphorus field-effect transistors (FETs) that have reconfigurable polarities are suitable for hardware security applications. The transistors can be dynamically switched between p-FET and n-FET operation through electrostatic gating and can achieve on–off ratios of 105 and subthreshold swings of 72 mV dec−1 at room temperature. Using the transistors, we create inverters that exhibit gains of 33.3 and are fully functional at a supply voltage of 0.2 V. We also create a security primitive circuit with polymorphic NAND/NOR obfuscation functionality with sub-1-V operation voltages, and the robustness of the polymorphic gate against power supply variations is tested using Monte Carlo simulations. Transistors that use two-dimensional black phosphorus as the active material can dynamically switch between p-type and n-type operation, and can be used to create security primitive circuits with polymorphic NAND/NOR obfuscation functionality.

Schottky barrier heights in two-dimensional field-effect transistors: from theory to experiment.

Abstract: Over the past decade, two-dimensional semiconductors (2DSCs) have aroused wide interest due to their extraordinary electronic, magnetic, optical, mechanical, and thermal properties, which hold potential in electronic, optoelectronic, thermoelectric applications, and so forth. The field-effect transistor (FET), a semiconductor gated with at least three terminals, is pervasively exploited as the device geometry for these applications. For lack of effective and stable substitutional doping techniques, direct metal contact is often used in 2DSC FETs to inject carriers. A Schottky barrier (SB) generally exists in the metal-2DSC junction, which significantly affects and even dominates the performance of most 2DSC FETs. Therefore, low SB or Ohmic contact is highly preferred for approaching the intrinsic characteristics of the 2DSC channel. In this review, we systematically introduce the recent progress made in theoretical prediction of the SB height (SBH) in the 2DSC FETs and the efforts made both in theory and experiments to achieve low SB contacts. From the comparison between the theoretical and experimentally observed SBHs, the emerging first-principles quantum transport simulation turns out to be the most powerful theoretical tool to calculate the SBH of a 2DSC FET. Finally, we conclude this review from the viewpoints of state-of-the-art electrode designs for 2DSC FETs.

Three-dimensional monolithic micro-LED display driven by atomically thin transistor matrix.

Abstract: Two-dimensional materials are promising candidates for future electronics due to unmatched device performance at atomic limit and low-temperature heterogeneous integration. To adopt these emerging materials in computing and optoelectronic systems, back end of line (BEOL) integration with mainstream technologies is needed. Here, we show the integration of large-area MoS2 thin-film transistors (TFTs) with nitride micro light-emitting diodes (LEDs) through a BEOL process and demonstrate high-resolution displays. The MoS2 transistors exhibit median mobility of 54 cm2 V−1s −1, 210 μA μm−1 drive current and excellent uniformity. The TFTs can drive micrometre-sized LEDs to 7.1 × 107 cd m−2 luminance under low voltage. Comprehensive analysis on driving capability, response time, power consumption and modulation scheme indicates that MoS2 TFTs are suitable for a range of display applications up to the high resolution and brightness limit. We further demonstrate prototypical 32 × 32 active-matrix displays at 1,270 pixels-per-inch resolution. Moreover, our process is fully monolithic, low-temperature, scalable and compatible with microelectronic processing. Low-temperature ultraclean integration of large-area MoS2 thin-film transistors with nitride micro-LEDs through a back end of line process enables the demonstration of displays with high resolution and uniformity.

High Current Density in Monolayer MoS2 Doped by AlOx.

Abstract: Semiconductors require stable doping for applications in transistors, optoelectronics, and thermoelectrics. However, this has been challenging for two-dimensional (2D) materials, where existing approaches are either incompatible with conventional semiconductor processing or introduce time-dependent, hysteretic behavior. Here we show that low-temperature ( 2 × 1013 cm-2, sheet resistance as low as ∼7 kΩ/□, and good contact resistance ∼480 Ω·μm in transistors from monolayer MoS2 grown by chemical vapor deposition. We also reach record current density of nearly 700 μA/μm (>110 MA/cm2) along this three-atom-thick semiconductor while preserving transistor on/off current ratio >106. The maximum current is ultimately limited by self-heating (SH) and could exceed 1 mA/μm with better device heat sinking. With their 0.1 nA/μm off-current, such doped MoS2 devices approach several low-power transistor metrics required by the international technology roadmap.

Recent Progress in Transistor-Based Optoelectronic Synapses: From Neuromorphic Computing to Artificial Sensory System

Abstract: Neuromorphic electronics draw attention as innovative approaches that facilitate hardware implementation of next‐generation artificial intelligent system including neuromorphic in‐memory computing, artificial sensory perception, and humanoid robotics. Among the various neuromorphic devices, optoelectronic synapses are promising neuromorphic devices that use optical means to mimic synaptic plasticity and related functions. Compared with classical neuromorphic chip based on electronic synapses using electrical means, photonic neuromorphic chip using light as input spike signal can be attractive alternative approach for next‐generation artificial intelligent system capable of high density, low power consumption, and low crosstalk. Thus, various optoelectronic synaptic electronics have been developed to overcome the drawback of conventional artificial intelligent system based on electrical synapses. Herein, the recent progresses in transistor‐based optoelectronic synapses for artificial intelligent system and review their device architecture, neuromorphic operational mechanisms, manufacturing methodologies, and advanced applications for artificial intelligent computing and visual perception systems are focused. Finally, the future challenges and research direction in the optoelectronic synaptic research are discussed.

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory

Abstract: Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

Van der Waals engineering of ferroelectric heterostructures for long-retention memory

Abstract: The limited memory retention for a ferroelectric field-effect transistor has prevented the commercialization of its nonvolatile memory potential using the commercially available ferroelectrics. Here, we show a long-retention ferroelectric transistor memory cell featuring a metal-ferroelectric-metal-insulator-semiconductor architecture built from all van der Waals single crystals. Our device exhibits 17 mV dec−1 operation, a memory window larger than 3.8 V, and program/erase ratio greater than 107. Thanks to the trap-free interfaces and the minimized depolarization effects via van der Waals engineering, more than 104 cycles endurance, a 10-year memory retention and sub-5 μs program/erase speed are achieved. A single pulse as short as 100 ns is enough for polarization reversal, and a 4-bit/cell operation of a van der Waals ferroelectric transistor is demonstrated under a 100 ns pulse train. These device characteristics suggest that van der Waals engineering is a promising direction to improve ferroelectronic memory performance and reliability for future applications. The memory retention for a ferroelectric field-effect transistor is limited by the depolarization effects and carrier charge trapping. Here, the authors fabricate a long-retention memory cell with a metal-ferroelectric-metal-insulator-semiconductor architecture built from all van der Waals single crystals.

Sub-thermionic, ultra-high-gain organic transistors and circuits

Abstract: The development of organic thin-film transistors (OTFTs) with low power consumption and high gain will advance many flexible electronics. Here, by combining solution-processed monolayer organic crystal, ferroelectric HfZrOx gating and van der Waals fabrication, we realize flexible OTFTs that simultaneously deliver high transconductance and sub-60 mV/dec switching, under one-volt operating voltage. The overall optimization of transconductance, subthreshold swing and output resistance leads to transistor intrinsic gain and amplifier voltage gain over 5.3 × 104 and 1.1 × 104, respectively, which outperform existing technologies using organics, oxides and low-dimensional nanomaterials. We further demonstrate battery-powered, integrated wearable electrocardiogram (ECG) and pulse sensors that can amplify human physiological signal by 900 times with high fidelity. The sensors are capable of detecting weak ECG waves (undetectable even by clinical equipment) and diagnosing arrhythmia and atrial fibrillation. Our sub-thermionic OTFT is promising for battery/wireless powered yet performance demanding applications such as electronic skins and radio-frequency identification tags, among many others.

An organic transistor with light intensity-dependent active photoadaptation

Abstract: The development of artificial visual systems that mimic biological systems requires devices that can autonomously adapt their response to varying stimuli. However, emulating biological feedforward visual adaptation is challenging and requires complementary photoexcitation and inhibition, ideally in a single device. Here we show that an organic transistor that incorporates two bulk heterojunctions is capable of light intensity-dependent active photoadaptation. The approach couples the photovoltaic effect in bulk heterojunctions with electron trapping in the dielectric layer, allowing adaptive modulation of the carrier concentration of the transistor. Our device exhibits active photoadaptation behaviour for light intensities ranging over six orders of magnitude (1 to 106 cd m−2). We also define an active adaptation index to describe the luminance-dependent changes to sensitivity, including auto-background control, which for our devices is comparable to that of the human visual system (less than 2 s at 1 × 104 cd m−2). An organic transistor that incorporates two bulk heterojunctions can exhibit active photoadaptation behaviour for light intensities that range over six orders of magnitude.

A Steep-Slope MoS2/Graphene Dirac-Source Field-Effect Transistor with a Large Drive Current

Abstract: In the continuous transistor feature size scaling down, the scaling of the supply voltage is stagnant because of the subthreshold swing (SS) limit. A transistor with a new mechanism is needed to break through the thermionic limit of SS and hold the large drive current at the same time. Here, by adopting the recently proposed Dirac-source field-effect transistor (DSFET) technology, we experimentally demonstrate a MoS2/graphene (1.8 nm/0.3 nm) DSFET for the first time, and a steep SS of 37.9 mV/dec at room temperature with nearly free hysteresis is observed. Besides, by bringing in the structure of gate-all-around (GAA), the MoS2/graphene DSFET exhibits a steeper SS of 33.5 mV/dec and a 40% increased normalized drive current up to 52.7 μA·μm/μm (VDS = 1 V) with a current on/off ratio of 108, which shows potential for low-power and high-performance electronics applications.

Performance of GaN Power Devices for Cryogenic Applications Down to 4.2 K

Abstract: Gallium nitride (GaN) power devices are employed in an increasing number of applications thanks to their excellent performance. Nevertheless, their potential for cryogenic applications, such as space, aviation, and superconducting systems, has not yet been fully explored. In particular, little is known on the device performance below liquid nitrogen temperature (77 K) and the behavior of popular GaN architectures such as gate injection transistor and Cascode below room temperature has not yet been reported. Most importantly, it is still unclear how the different device loss contributions, i.e., conduction, soft- and hard-switching losses, change at cryogenic temperatures. In this letter, we investigate and compare the performance of four GaN commercial power devices in a wide temperature range between 400 and 4.2 K. All of the tested devices can successfully operate at cryogenic temperatures with an overall performance improvement. However, different GaN HEMT technologies lead to significant variations in device gate control and loss mechanisms, which are discussed based on the device structure. The presented results prove the promising potential of the GaN technology for low-temperature applications and provide precious insights to properly design power systems operating under cryogenic temperatures and maximize their efficiency.

Electronics based on two-dimensional materials: Status and outlook

Abstract: Since Moore’s law in the traditional semiconductor industry is facing shocks, More Moore and More than Moore are proposed as two paths to maintain the development of the semiconductor industry by adopting new architectures or new materials, in which the former is committed to the continued scaling of transistors for performance enhancement, and the latter pursues the realization of functional diversification of electronic systems. Two-dimensional (2D) materials are supposed to play an important role in these two paths. In More Moore, the ultimate thin thickness and the dangling-bond-free surface of 2D channels offer excellent gate electrostatics while avoiding the degradation of carrier mobility at the same time, so that the transistors can be further scaled down for higher performance. In More than Moore, devices based on 2D materials can well meet the requirements of electronic systems for functional diversity, like that they can operate at high frequency, exhibit excellent sensitivity to the changes in the surroundings at room temperature, have good mechanical flexibility, and so on. In this review, we present the application of 2D materials in More Moore and More than Moore domains of electronics, outlining their potential as a technological option for logic electronics, memory electronics, radio-frequency electronics, sensing electronics, and flexible electronics.

Negative capacitance effects in ferroelectric heterostructures: A theoretical perspective

Abstract: In a heterogeneous system, ferroelectric materials can exhibit negative capacitance (NC) behavior given that the overall capacitance of the system remains positive. Such NC effects may lead to differential amplification in local potential and can provide an enhanced charge and capacitance response for the whole system compared to their constituents. Such intriguing implications of NC phenomena have prompted the design and exploration of many ferroelectric-based electronic devices to not only achieve an improved performance but potentially also overcome some fundamental limits of standard transistors. However, the microscopic physical origin as well as the true nature of the NC effect, and direct experimental evidence remain elusive and debatable. To that end, in this article, we provide a comprehensive theoretical perspective on the current understanding of the underlying physical mechanism of the NC effect in the ferroelectric material. Based upon the fundamental physics of ferroelectric material, we discuss different assumptions, conditions, and distinct features of the quasi-static NC effect in the single-domain and multi-domain scenarios. While the quasi-static and hysteresis-free NC effect was initially propounded in the context of a single-domain scenario, we highlight that similar effects can be observed in multi-domain FEs with soft domain-wall (DW) displacement. Furthermore, to obtain the soft-DW, the gradient energy coefficient of the FE material is required to be higher as well as the ferroelectric thickness is required to be lower than some critical values. If those requirements are not met, then the DW becomes hard and their displacement would lead to hysteretic NC effects, which are adiabatically irreversible. In addition to the quasi-static NC, we discuss different mechanisms that can potentially lead to the transient NC effects. Furthermore, we discuss different existing experimental results by correlating their distinct features with different types of NC attributes and provide guidelines for new experiments that can potentially provide new insights on unveiling the real origin of NC phenomena.

Graphene film for thermal management: A review

Abstract: Thermal conductivity and thermal dissipation are of great importance for modern electronics due to the increased transistor density and operation frequency of contemporary integrated circuits. Due to its exceptionally high thermal conductivity, graphene has drawn considerable interests worldwide for heat spreading and dissipation. However, maintaining high thermal conductivity in graphene laminates (the basic technological unit) is a significant technological challenge. Aiming at highly thermal conductive graphene films (GFs), this prospective review outlines the most recent progress in the production of GFs originated from graphene oxide due to its great convenience in film processing. Additionally, we also consider such issues as film assembly, defect repair and mechanical compression during the post-treatment. We also discuss the thermal conductivity in in-plane and through-plane direction and mechanical properties of GFs. Further, the current typical applications of GFs are presented in thermal management. Finally, perspectives are given for future work on GFs for thermal management.

Ferroelectric Field Effect Transistors as a Synapse for Neuromorphic Application

Abstract: In spite of the increasing use of machine learning techniques, in-memory computing and hardware have increased the interest to accelerate neural network operation Henceforth, novel embedded nonvolatile memories (eNVMs) for highly scaled technology nodes, like ferroelectric field effect transistors (FeFETs), are heavily studied and very promising Furthermore, inference and on-chip learning can be fostered by further eNVM technology options, such as multibit operation and linear switching In this article, we present the advantages of hafnium oxide-based FeFETs for such purposes due to their basic three-terminal structure, which allows to selectively activate or deactivate selected devices as well as tune linearity and dynamic range for certain applications Furthermore, we discuss the impact of the material properties of the ferroelectric layer, the interface layer thickness, and scaling on the device performance Here, we demonstrate good device properties even for highly scaled devices ( $100\,\,nm \times 100$ nm)

Sensitivity of Field-Effect Transistor-Based Terahertz Detectors

Abstract: This paper presents an overview of the different methods used for sensitivity (i.e., responsivity and noise equivalent power) determination of state-of-the-art field-effect transistor-based THz detectors/sensors. We point out that the reported result may depend very much on the method used to determine the effective area of the sensor, often leading to discrepancies of up to orders of magnitude. The challenges that arise when selecting a proper method for characterisation are demonstrated using the example of a 2×7 detector array. This array utilises field-effect transistors and monolithically integrated patch antennas at 620 GHz. The directivities of the individual antennas were simulated and determined from the measured angle dependence of the rectified voltage, as a function of tilting in the E- and H-planes. Furthermore, this study shows that the experimentally determined directivity and simulations imply that the part of radiation might still propagate in the substrate, resulting in modification of the sensor effective area. Our work summarises the methods for determining sensitivity which are paving the way towards the unified scientific metrology of FET-based THz sensors, which is important for both researchers competing for records, potential users, and system designers.

Design and Analysis of Modified Pre-Charge Sensing Circuit for STT-MRAM

Abstract: A non-volatile memory designed to FLASH recollections and switch SRAM seems to be the Magnetic RAM (MRAM) proximity unit. Due to its inherent radiation hardness, Spin Transfer Torque Magnetic Memory (STT-MRAM) was also used for top-responsibility applications. CMOS circuit sensitive to radiation Pre Charge Sense electronic equipment (PCSA); but we are able to recharge the non-volatile storage ceaselessly to urge accurate details. Since the current advantages are abandoned by radiation effects, STT-MRAM cannot be used specifically for top radiation applications. In this paper, a new style in the change of PCSA STT-MRAM sensing circuit is proposed and the paper focused more on power and space with performance up gradation.

Multiresponsive nonvolatile memories based on optically switchable ferroelectric organic field-effect transistors

Abstract: Organic transistors are key elements for flexible, wearable, and biocompatible logic applications. Multiresponsivity is highly sought-after in organic electronics to enable sophisticated operations and functions. Such a challenge can be pursued by integrating more components in a single device, each one responding to a specific external stimulus. Here, the first multiresponsive organic device based on a photochromic-ferroelectric organic field-effect transistor, which is capable of operating as nonvolatile memory with 11 bit memory storage capacity in a single device, is reported. The memory elements can be written and erased independently by means of light or an electric field, with accurate control over the readout signal, excellent repeatability, fast response, and high retention time. Such a proof of concept paves the way toward enhanced functional complexity in optoelectronics via the interfacing of multiple components in a single device, in a fully integrated low-cost technology compatible with flexible substrates.

Recent advanced applications of ion-gel in ionic-gated transistor

Abstract: Diversified regulation of electrons have received much attention to realize a multi-functional transistor, and it is crucial to have a considerable control over the charge carriers in transistors. Ionic gel, as the dielectric material in transistors, facilitates a large capacitance, and high induced-carrier concentrations. This review presents the recent progress in ionic-gated transistors (IGTs) that have good mechanical stability as well as high physical and chemical stability. We first briefly introduce the various applications of IGTs in sensors, neuromorphic transistors, organic transistor circuits, and health detection. Finally, the future perspectives of IGTs are discussed and some possible solutions to the challenges are also proposed.

Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs

Abstract: Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates can diminish these advantages in practice. In this brief, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units.

Realizing High-Performance β-Ga₂O₃ MOSFET by Using Variation of Lateral Doping: A TCAD Study

Abstract: In this article, for the first time, a variation of lateral doping (VLD) technique was proposed to improve blocking voltage and ON-resistance properties in the lateral $\beta $ -Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET). Enhancement-mode operation was achieved in the VLD transistor. The maximum transconductance of this new device is more than three times as large as the uniformly doped (UD) transistor. Moreover, the OFF-state electric field at the channel was suppressed compared to the UD transistor, resulting in higher blocking voltage. We also investigated the optimal device properties with changing channel concentration in the drift region of VLD transistor. A power figure of merit of 332.7 MW/cm2 was reached by VLD design. Thus, this proposed structure provides a new design strategy for high-power $\beta $ -Ga2O3 MOSFETs.

High-performance polymer field-effect transistors: from the perspective of multi-level microstructures

Abstract: The multi-level microstructure of conjugated polymers is the most critical parameter determining the charge transport property in field-effect transistors (FETs). However, controlling the hierarchical microstructures and the structural evolution remains a significant challenge. In this perspective, we discuss the key aspects of multi-level microstructures of conjugated polymers towards high-performance FETs. We highlight the recent progress in the molecular structures, solution-state aggregation, and polymer crystal structures, representing the multi-level microstructures of conjugated polymers. By tuning polymer hierarchical microstructures, we attempt to provide several guidelines for developing high-performance polymer FETs and polymer electronics.