Showing papers on "Wafer published in 2021"

Epitaxial growth of wafer-scale molybdenum disulfide semiconductor single crystals on sapphire

Abstract: Two-dimensional (2D) semiconductors, in particular transition metal dichalcogenides (TMDCs), have attracted great interest in extending Moore’s law beyond silicon1–3. However, despite extensive efforts4–25, the growth of wafer-scale TMDC single crystals on scalable and industry-compatible substrates has not been well demonstrated. Here we demonstrate the epitaxial growth of 2 inch (~50 mm) monolayer molybdenum disulfide (MoS2) single crystals on a C-plane sapphire. We designed the miscut orientation towards the A axis (C/A) of sapphire, which is perpendicular to the standard substrates. Although the change of miscut orientation does not affect the epitaxial relationship, the resulting step edges break the degeneracy of nucleation energy for the antiparallel MoS2 domains and lead to more than a 99% unidirectional alignment. A set of microscopies, spectroscopies and electrical measurements consistently showed that the MoS2 is single crystalline and has an excellent wafer-scale uniformity. We fabricated field-effect transistors and obtained a mobility of 102.6 cm2 V−1 s−1 and a saturation current of 450 μA μm–1, which are among the highest for monolayer MoS2. A statistical analysis of 160 field-effect transistors over a centimetre scale showed a >94% device yield and a 15% variation in mobility. We further demonstrated the single-crystalline MoSe2 on C/A sapphire. Our method offers a general and scalable route to produce TMDC single crystals towards future electronics. Unidirectional alignment of MoS2 domains during epitaxial growth on C/A sapphire enables the realization of large-area MoS2 single crystals.

Single-crystal hexagonal boron nitride monolayer epitaxially grown on Cu (111) thin film across a wafer

Abstract: We demonstrate single crystal growth of wafer-scale hexagonal boron nitride (hBN), an insulating atomic thin monolayer, on high-symmetry index surface plane Cu(111). The unidirectional epitaxial growth is guaranteed by large binding energy difference, ~0.23 eV, between A- and B-steps edges on Cu(111) docking with B6N7 clusters, confirmed by density functional theory calculations.

Seeded 2D epitaxy of large-area single-crystal films of the van der Waals semiconductor 2H MoTe 2

Abstract: The integration of two-dimensional (2D) van der Waals semiconductors into silicon electronics technology will require the production of large-scale, uniform, and highly crystalline films We report a route for synthesizing wafer-scale single-crystalline 2H molybdenum ditelluride (MoTe2) semiconductors on an amorphous insulating substrate In-plane 2D-epitaxy growth by tellurizing was triggered from a deliberately implanted single seed crystal The resulting single-crystalline film completely covered a 25-centimeter wafer with excellent uniformity The 2H MoTe2 2D single-crystalline film can use itself as a template for further rapid epitaxy in a vertical manner Transistor arrays fabricated with the as-prepared 2H MoTe2 single crystals exhibited high electrical performance, with excellent uniformity and 100% device yield

Supersaturation-Controlled Growth of Monolithically Integrated Lead-Free Halide Perovskite Single-Crystalline Thin Film for High-Sensitivity Photodetectors.

Abstract: Monolithical integration of the promising optoelectronic material with mature and inexpensive silicon circuitry contributes to simplifying device geometry, enhancing performance, and expanding new functionalities. Herein, a lead-free halide perovskite Cs3 Bi2 I9 single-crystalline thin film (SCTF), with thickness ranging from 900 nm to 4.1 µm and aspect ratio up to 1666, is directly integrated on various substrates including Si wafer, through a facile and low-temperature solution-processing method. The growth kinetics of the lead-free halide perovskite SCTF are elucidated by in situ observation, and the solution supersaturation is controlled to reduce the inverse-temperature crystallization nucleation density and elongate the evaporation growth. The excellent lattice match and band alignment between Si(111) and Cs3 Bi2 I9 (001) facets promote photogenerated charge dissociation and extraction, resulting in boosting the photoelectric sensitivity by 10-200 times compared with photodetectors based on other substrates. More importantly, this silicon-compatible perovskite SCTF photodetector exhibits a high switching ratio of 3000 and a fast response of 1.5 µs, which are higher than most reported state-of-the-art lead-free halide perovskite photodetectors. This work not only gives an in-depth understanding of the perovskite precursor solution chemistry, but also demonstrates the great potential of monolithical integration of lead-free halide perovskite SCTF with a silicon wafer for high-performance photodetectors.

Large-area integration of two-dimensional materials and their heterostructures by wafer bonding

Abstract: Integrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to [Formula: see text]. Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing.

Wafer-scale growth of two-dimensional graphitic carbon nitride films

Abstract: Summary The extension of graphitic carbon nitride (g-CN) materials into optoelectronic applications beyond photocatalysis has long been anticipated due to their non-metallic composition, moderate electronic band gap, and excellent stability. However, large-scale synthesis of uniform two-dimensional (2D) g-CN films with high crystallinity and tunable thickness remains the bottleneck for their future applications in optoelectronic devices. Here, a vapor-phase transport-assisted condensation method has been developed for the wafer-scale synthesis of uniform 2D g-CN films with tunable thickness. First-principle calculations indicate the direct condensation from melem to heptazine-based carbon nitride enables the formation of high-quality g-CN films. A facile water-assisted transfer strategy is developed for subsequent fabrication on arbitrary substrate. A free-standing flexible photodetector array with strain-insensitive responsibility is demonstrated with the g-CN films as imaging pixels. This study provides a convenient route to wafer-scale growth of high-quality 2D g-CN films and paves the way to the g-CN-based electronic and optoelectronic devices.

Impact of 2D-3D Heterointerface on Remote Epitaxial Interaction through Graphene.

Abstract: Remote epitaxy has drawn attention as it offers epitaxy of functional materials that can be released from the substrates with atomic precision, thus enabling production and heterointegration of flexible, transferrable, and stackable freestanding single-crystalline membranes. In addition, the remote interaction of atoms and adatoms through two-dimensional (2D) materials in remote epitaxy allows investigation and utilization of electrical/chemical/physical coupling of bulk (3D) materials via 2D materials (3D-2D-3D coupling). Here, we unveil the respective roles and impacts of the substrate material, graphene, substrate-graphene interface, and epitaxial material for electrostatic coupling of these materials, which governs cohesive ordering and can lead to single-crystal epitaxy in the overlying film. We show that simply coating a graphene layer on wafers does not guarantee successful implementation of remote epitaxy, since atomically precise control of the graphene-coated interface is required, and provides key considerations for maximizing the remote electrostatic interaction between the substrate and adatoms. This was enabled by exploring various material systems and processing conditions, and we demonstrate that the rules of remote epitaxy vary significantly depending on the ionicity of material systems as well as the graphene-substrate interface and the epitaxy environment. The general rule of thumb discovered here enables expanding 3D material libraries that can be stacked in freestanding form.

Wafer-Scale Lateral Self-Assembly of Mosaic Ti3C2Tx MXene Monolayer Films.

Abstract: Bottom-up assembly of two-dimensional (2D) materials into macroscale morphologies with emergent properties requires control of the material surroundings, so that energetically favorable conditions direct the assembly process. MXenes, a class of recently developed 2D materials, have found new applications in areas such as electrochemical energy storage, nanoscale electronics, sensors, and biosensors. In this paper, we present a lateral self-assembly method for wafer-scale deposition of a mosaic-type 2D MXene flake monolayer that spontaneously orders at the interface between two immiscible solvents. ReaxFF molecular dynamics simulations elucidate the interactions of a MXene flake with the solvents and its stability at the liquid/liquid interface, the prerequisite for MXene flakes self-assembly at the interface. Moreover, facile transfer of this monolayer onto a flat substrate (Si, glass) results in high-coverage monolayer films with uniform thickness and homogeneous optical properties. Multiscale characterization of the resulting films reveals the mosaic structure and sheds light on the electronic properties of the films, which exhibit good electrical conductivity over cm-scale areas.

Defect characterization and charge transport measurements in high-resolution Ni/n-4H-SiC Schottky barrier radiation detectors fabricated on 250 μm epitaxial layers

Abstract: Advances in the growth processes of 4H-SiC epitaxial layers have led to the continued expansion of epilayer thickness, allowing for the detection of more penetrative radioactive particles. We report the fabrication and characterization of high-resolution Schottky barrier radiation detectors on 250 μm thick n-type 4H-SiC epitaxial layers, the highest reported thickness to date. Several 8 × 8 mm2 detectors were fabricated from a diced 100 mm diameter 4H-SiC epitaxial wafer grown on a conductive 4H-SiC substrate with a mean micropipe density of 0.11 cm−2. From the Mott–Schottky plots, the effective doping concentration was found to be in the range (0.95–1.85) × 1014 cm−3, implying that full depletion could be achieved at ∼5.7 kV (0.5 MV/cm at the interface). The current-voltage characteristics demonstrated consistently low leakage current densities of 1–3 nA/cm2 at a reverse bias of −800 V. This resulted in the pulse-height spectra generated using a 241Am alpha source (5486 keV) manifesting an energy resolution of less than 0.5% full width at half maximum (FWHM) for all the detectors at −200 V. The charge collection efficiencies (CCEs) were measured to be 98–99% with no discernable correlation to the energy resolution. A drift-diffusion model fit to the variation of CCE as a function of bias voltage, revealed a minority carrier diffusion length of ∼10 μm. Deep level transient spectroscopy measurements on the best resolution detector revealed that the excellent performance was the result of having ultralow concentrations of the order of 1011 cm−3 lifetime limiting defects—Z1/2 and EH6/7.

From Crystalline to Low-cost Silicon-based Solar Cells: a Review

Abstract: Renewable energy has become an auspicious alternative to fossil fuel resources due to its sustainability and renewability. In this respect, Photovoltaics (PV) technology is one of the essential technologies. Today, more than 90 % of the global PV market relies on crystalline silicon (c-Si)-based solar cells. This article reviews the dynamic field of Si-based solar cells from high-cost crystalline to low-cost cells and investigates how to preserve high possible efficiencies while decreasing the cost. First, we discuss the various types of c-Si solar cells with different device architectures and report recent developments. Next, thin-film solar cells with their recent advancements are given. Then, Si nanowires solar cells and their recent results are discussed. Finally, we present the most encouraging tendencies in achieving low-cost solar cells utilizing cheap materials like heavily doped silicon wafers.

Post-Fabrication Trimming of Silicon Photonic Ring Resonators at Wafer-Scale

Abstract: Silicon ring resonator-based devices, such as modulators, detectors, filters, and switches, play important roles in integrated photonic circuits for optical communication, high-performance computing, and sensing applications. However, the high sensitivity to fabrication variations has limited their volume manufacturability and commercial adoption. Here, we report a low-cost post-fabrication trimming method to tune the resonance wavelength of a silicon ring resonator and correct for fabrication variations at wafer-scale. We use Ge implant to create an index trimmable section in the ring resonator and an on-chip heater to apply a precise and localized thermal annealing to tune and set its resonance to a desired wavelength. We demonstrate resonance wavelength trimming of ring resonators fabricated across a 300 mm silicon-on-insulator (SOI) wafer to within p32 pm of a target wavelength of 1310 nm, providing a viable path to high-volume manufacturing and opening up new practical applications for these devices.

Heterogeneous Wafer Bonding Technology and Thin-Film Transfer Technology-Enabling Platform for the Next Generation Applications beyond 5G.

Abstract: Wafer bonding technology is one of the most effective methods for high-quality thin-film transfer onto different substrates combined with ion implantation processes, laser irradiation, and the removal of the sacrificial layers. In this review, we systematically summarize and introduce applications of the thin films obtained by wafer bonding technology in the fields of electronics, optical devices, on-chip integrated mid-infrared sensors, and wearable sensors. The fabrication of silicon-on-insulator (SOI) wafers based on the Smart CutTM process, heterogeneous integrations of wide-bandgap semiconductors, infrared materials, and electro-optical crystals via wafer bonding technology for thin-film transfer are orderly presented. Furthermore, device design and fabrication progress based on the platforms mentioned above is highlighted in this work. They demonstrate that the transferred films can satisfy high-performance power electronics, molecular sensors, and high-speed modulators for the next generation applications beyond 5G. Moreover, flexible composite structures prepared by the wafer bonding and de-bonding methods towards wearable electronics are reported. Finally, the outlooks and conclusions about the further development of heterogeneous structures that need to be achieved by the wafer bonding technology are discussed.

Broad Diversity of Near-Infrared Single-Photon Emitters in Silicon.

Abstract: We report the detection of individual emitters in silicon belonging to seven different families of optically active point defects. These fluorescent centers are created by carbon implantation of a commercial silicon- on-insulator wafer usually employed for integrated photonics. Single photon emission is demonstrated over the 1.1–1.55 μm range, spanning the O and C telecom bands. We analyze their photoluminescence spectra, dipolar emissions, and optical relaxation dynamics at 10 K. For a specific family, we show a constant emission intensity at saturation from 10 K to temperatures well above the 77 K liquid nitrogen temperature. Given the advanced control over nanofabrication and integration in silicon, these individual artificial atoms are promising systems to investigate for Si-based quantum technologies.

Ga2O3-on-SiC Composite Wafer for Thermal Management of Ultrawide Bandgap Electronics.

Abstract: β-phase gallium oxide (Ga2O3) is an emerging ultrawide bandgap (UWBG) semiconductor (EG ∼ 4.8 eV), which promises generational improvements in the performance and manufacturing cost over today's commercial wide bandgap power electronics based on GaN and SiC. However, overheating has been identified as a major bottleneck to the performance and commercialization of Ga2O3 device technologies. In this work, a novel Ga2O3/4H-SiC composite wafer with high heat transfer performance and an epi-ready surface finish has been developed using a fusion-bonding method. By taking advantage of low-temperature metalorganic vapor phase epitaxy, a Ga2O3 epitaxial layer was successfully grown on the composite wafer while maintaining the structural integrity of the composite wafer without causing interface damage. An atomically smooth homoepitaxial film with a room-temperature Hall mobility of ∼94 cm2/Vs and a volume charge of ∼3 × 1017 cm-3 was achieved at a growth temperature of 600 °C. Phonon transport across the Ga2O3/4H-SiC interface has been studied using frequency-domain thermoreflectance and a differential steady-state thermoreflectance approach. Scanning transmission electron microscopy analysis suggests that phonon transport across the Ga2O3/4H-SiC interface is dominated by the thickness of the SiNx bonding layer and an unintentionally formed SiOx interlayer. Extrinsic effects that impact the thermal conductivity of the 6.5 μm thick Ga2O3 layer were studied via time-domain thermoreflectance. Thermal simulation was performed to estimate the improvement of the thermal performance of a hypothetical single-finger Ga2O3 metal-semiconductor field-effect transistor fabricated on the composite substrate. This novel power transistor topology resulted in a ∼4.3× reduction in the junction-to-package device thermal resistance. Furthermore, an even more pronounced cooling effect is demonstrated when the composite wafer is implemented into the device design of practical multifinger devices. These innovations in device-level thermal management give promise to the full exploitation of the promising benefits of the UWBG material, which will lead to significant improvements in the power density and efficiency of power electronics over current state-of-the-art commercial devices.

Gallium-Doped Silicon for High-Efficiency Commercial Passivated Emitter and Rear Solar Cells

Abstract: Czochralski‐grown gallium‐doped silicon wafers are now a mainstream substrate for commercial passivated emitter and rear cell (PERC) devices and allow retention of established processes while offering enhanced cell stability. We have assessed the carrier lifetime potential of such Czochralski‐grown wafers in dependence of resistivity, finding effective lifetimes well into the millisecond region without any gettering or hydrogenation processing, thus demonstrating one advantage over boron‐doped silicon. Second, the stability of gallium‐doped PERC cells are monitored under illumination (>3000 h in some cases) and anomalous behavior is detected. While some cells are stable, others exhibit a degradation then recovery, reminiscent of light and elevated temperature‐induced degradation (LeTID) observed in other silicon materials. Surprisingly, cells from one ingot exhibit LeTID‐like behavior when annealed at 300 °C but near stability when not annealed, but, for another ingot, the opposite is observed. Moreover, a stabilization process typically used to mitigate boron–oxygen degradation does not influence any cells that are studied. Secondary‐ion mass spectrometry of the PERC cells reveals significant concentrations of unintentionally incorporated boron in some cases. Nevertheless, even in the absence of mitigating light‐induced degradation, Ga‐doped silicon is still more stable than unstabilized B‐doped silicon under illumination.

Aligned 2D carbon nanotube liquid crystals for wafer-scale electronics.

Abstract: Semiconducting carbon nanotubes promise faster performance and lower power consumption than Si in field-effect transistors (FETs) if they can be aligned in dense arrays. Here, we demonstrate that n...

Reducing Wafer Delay Time by Robot Idle Time Regulation for Single-Arm Cluster Tools

Abstract: Nowadays, wafer fabrication in semiconductor manufacturing is highly dependent on cluster tools. A cluster tool is equipped with several process modules (PMs) and a wafer handling robot. When the tool is operating, generally each PM is processing a wafer, and the robot is responsible for delivering the wafers from one PM to another. Thus, when a wafer is completed in a PM, the robot may be busy for performing other tasks such that it cannot immediately unload the completed wafer in the PM, resulting in that the wafer has to stay there for some extra time. The processing time of a wafer together with its delay time for waiting for the robot’s arrival for unloading is defined as wafer residency time in a PM. However, a long wafer delay time may deteriorate its quality. Therefore, it is highly desired and important to reduce the wafer delay time at each step as much as possible. This work aims to tackle this important issue for single-arm cluster tools (SACTs). Specifically, by using a Petri net model, this work analyzes the steady-state operational behavior of an SACT under the backward and earliest starting strategies. It is found that there must exist wafer delay time at the steps in the upstream of the bottleneck step, and such wafer delay time can be reduced by properly adjusting the robot waiting time. Thus, three algorithms are developed to reduce the wafer delay time at each step as much as possible by properly assigning the robot idle time. Finally, the application of the proposed method is illustrated by using examples. Note to Practitioners —In a modern semiconductor fab, there are hundreds of cluster tools for wafer fabrication. To ensure wafer quality, it is important to reduce the wafer delay time in PMs of cluster tools after a wafer is processed since the high temperature, chemical gas, and particles in the PMs may damage the wafer. To do so, this work proposes three algorithms with polynomial complexity to assign the robot idle time as robot waiting time such that the wafer delay time in PMs can be reduced as much as possible. Furthermore, the obtained schedule by these algorithms is optimal in terms of the cycle time. Besides, the developed algorithms can be easily embedded into the controller of cluster tools by facility engineers. Therefore, this work has a practical value.

Machine Learning-Based Detection Method for Wafer Test Induced Defects

Abstract: Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may induce defects to otherwise good dies. Test-induced defects not only hurt overall manufacturing yield but also create problems for yield learning, so the source problems in testing should be identified quickly. In the wafer acceptance test process, dies are probed in a predetermined order, so test-induced defects, also known as site-dependent faults, exhibit specific patterns that can be effectively captured in test paths. In this paper, we analyze characteristics of test-induced defect patterns and define features that can be used by machine learning algorithms for the automatic detection of test-induced defects. Therefore, defective dies caused by the wafer test can be retested for yield improvement. Test data from six real products are used to validate the proposed method. Several machine learning algorithms have been applied, and experimental results show that our method is effective to distinguish between test-induced and fabrication-induced defects. On average, the prediction accuracy is higher than 97%.

Wafer‐Scale Fabrication of 2D β‐In2Se3 Photodetectors

Abstract: The epitaxial growth of two-dimensional (2D) $\beta-In_2Se_3$ material was obtained over 2-inches c-sapphire wafers using molecular beam epitaxy (MBE). Excellent quality of thick (90 nm) and very thin films, down to two quintuple layers (2 nm), was confirmed by x-ray diffraction (XRD), Raman spectroscopy, and aberration-corrected scanning transmission electron microscopy (ac-STEM). Wafer-scale fabrication of photodetectors based on five quintuple layers was produced using photolithography and other standard semiconductor processing methods. The photodetectors exhibit responsivity of 3 mA/W, peak specific detectivity (D*) of $10^9$ Jones, external quantum efficiency (EQE) of 0.67 % at 550 nm, and response-time of ~7 ms, which is faster than any result previously reported for $\beta-In_2Se_3$ photodetectors. From the photocurrent measurements, an optical bandgap of 1.38 eV was observed. These results on wafer-scale deposition of 2D $In_2Se_3$, as well as its fabrication into optoelectronic devices provide the missing link that will enable the commercialization of 2D materials.

Graphene Buffer Layer on SiC as a Release Layer for High-Quality Freestanding Semiconductor Membranes

Abstract: Free-standing crystalline membranes are highly desirable owing to recent developments in heterogeneous integration of dissimilar materials. Van der Waals (vdW) epitaxy enables the release of crystalline membranes from their substrates. However, suppressed nucleation density due to low surface energy has been a challenge for crystallization; reactive materials synthesis environments can induce detrimental damage to vdW surfaces, often leading to failures in membrane release. This work demonstrates a novel platform based on graphitized SiC for fabricating high-quality free-standing membranes. After mechanically removing epitaxial graphene on a graphitized SiC wafer, the quasi-two-dimensional graphene buffer layer (GBL) surface remains intact for epitaxial growth. The reduced vdW gap between the epilayer and substrate enhances epitaxial interaction, promoting remote epitaxy. Significantly improved nucleation and convergent quality of GaN are achieved on the GBL, resulting in the best quality GaN ever grown on two-dimensional materials. The GBL surface exhibits excellent resistance to harsh growth environments, enabling substrate reuse by repeated growth and exfoliation.

Wafer-Scale Production of Transition Metal Dichalcogenides and Alloy Monolayers by Nanocrystal Conversion for Large-Scale Ultrathin Flexible Electronics.

Abstract: Two-dimensional (2D) transition metal dichalcogenide (TMD) layers are unit-cell thick materials with tunable physical properties according to their size, morphology, and chemical composition. Their transition of lab-scale research to industrial-scale applications requires process development for the wafer-scale growth and scalable device fabrication. Herein, we report on a new type of atmospheric pressure chemical vapor deposition (APCVD) process that utilizes colloidal nanoparticles as process-scalable precursors for the wafer-scale production of TMD monolayers. Facile uniform distribution of nanoparticle precursors on the entire substrate leads to the wafer-scale uniform synthesis of TMD monolayers with the controlled size and morphology. Composition-controlled TMD alloy monolayers with tunable bandgaps can be produced by simply mixing dual nanoparticle precursor solutions in the desired ratio. We also demonstrate the fabrication of ultrathin field-effect transistors and flexible electronics with uniformly controlled performance by using TMD monolayers.

Van der Waals epitaxy of nearly single-crystalline nitride films on amorphous graphene-glass wafer.

Abstract: Van der Waals epitaxy provides a fertile playground for the monolithic integration of various materials for advanced electronics and optoelectronics. Here, a previously unidentified nanorod-assisted van der Waals epitaxy is developed and nearly single-crystalline GaN films are first grown on amorphous silica glass substrates using a graphene interfacial layer. The epitaxial GaN-based light-emitting diode structures, with a record internal quantum efficiency, can be readily lifted off, becoming large-size flexible devices. Without the effects of the potential field from a single-crystalline substrate, we expect this approach to be equally applicable for high-quality growth of nitrides on arbitrary substrates. Our work provides a revolutionary technology for the growth of high-quality semiconductors, thus enabling the hetero-integration of highly mismatched material systems.

Direct growth of wafer-scale highly oriented graphene on sapphire.

Abstract: Direct chemical vapor deposition (CVD) growth of wafer-scale high-quality graphene on dielectrics is of paramount importance for versatile applications. Nevertheless, the synthesized graphene is ty...

Achieving a sub-10 nm nanopore array in silicon by metal-assisted chemical etching and machine learning

Abstract: Solid-state nanopores with controllable pore size and morphology have huge application potential. However, it has been very challenging to process sub-10 nm silicon nanopore arrays with high efficiency and high quality at low cost. In this study, a method combining metal-assisted chemical etching and machine learning is proposed to fabricate sub-10 nm nanopore arrays on silicon wafers with various dopant types and concentrations. Through a SVM algorithm, the relationship between the nanopore structures and the fabrication conditions, including the etching solution, etching time, dopant type, and concentration, was modeled and experimentally verified. Based on this, a processing parameter window for generating regular nanopore arrays on silicon wafers with variable doping types and concentrations was obtained. The proposed machine-learning-assisted etching method will provide a feasible and economical way to process high-quality silicon nanopores, nanostructures, and devices.