Showing papers on "Low-power electronics published in 2013"

State of the Art of Finite Control Set Model Predictive Control in Power Electronics

Abstract: This paper addresses to some of the latest contributions on the application of Finite Control Set Model Predictive Control (FCS-MPC) in Power Electronics. In FCS-MPC , the switching states are directly applied to the power converter, without the need of an additional modulation stage. The paper shows how the use of FCS-MPC provides a simple and efficient computational realization for different control objectives in Power Electronics. Some applications of this technology in drives, active filters, power conditioning, distributed generation and renewable energy are covered. Finally, attention is paid to the discussion of new trends in this technology and to the identification of open questions and future research topics.

Low-Power Far-Field Wireless Powering for Wireless Sensors

Abstract: This paper discusses far-field wireless powering for low-power wireless sensors, with applications to sensing in environments where it is difficult or impossible to change batteries and where the exact position of the sensors might not be known. With expected radio-frequency (RF) power densities in the 20-200- μW/cm2 range, and desired small sensor overall size, low-power nondirective wireless powering is appropriate for sensors that transmit data at low duty cycles. The sensor platform is powered through an antenna which receives incident electromagnetic waves in the gigahertz frequency range, couples the energy to a rectifier circuit which charges a storage device (e.g., thin-film battery) through an efficient power management circuit, and the entire platform, including sensors and a low-power wireless transmitter, and is controlled through a low-power microcontroller. For low incident power density levels, codesign of the RF powering and the power management circuits is required for optimal performance. Results for hybrid and monolithic implementations of the power management circuitry are presented with integrated antenna rectifiers operating in the 1.96-GHz cellular and in 2.4-GHz industrial-scientific-medical (ISM) bands.

A Modular 1 mm $^{3}$ Die-Stacked Sensing Platform With Low Power I $^{2}$ C Inter-Die Communication and Multi-Modal Energy Harvesting

Abstract: A 1.0 mm3 general-purpose sensor node platform with heterogeneous multi-layer structure is proposed. The sensor platform benefits from modularity by allowing the addition/removal of IC layers. A new low power I2C interface is introduced for energy efficient inter-layer communication with compatibility to commercial I2C protocols. A self-adapting power management unit is proposed for efficient battery voltage down conversion for wide range of battery voltages and load current. The power management unit also adapts itself by monitoring energy harvesting conditions and harvesting sources and is capable of harvesting from solar, thermal and microbial fuel cells. An optical wakeup receiver is proposed for sensor node programming and synchronization with 228 pW standby power. The system also includes two processors, timer, temperature sensor, and low-power imager. Standby power of the system is 11 nW.

A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications

Abstract: A 60GHz short-range wireless system offers new opportunities for achieving wireless high-definition video links and multi-Gb/s wireless data transfer. Recent works have realized a 60GHz transceiver by means of a cost-effective CMOS process [1-3], but using a 60GHz system in mobile terminals poses the difficult challenge of achieving low power consumption as well as small form factor. The publication [3] achieves a power consumption of less than 756mW, but uses a simple MAC protocol incompatible with global standards and also suffers from a limited distance of less than 4cm. This paper presents a fully integrated transceiver chipset based on WiGig/IEEE802.11ad standards targeting mobile usage. The chipset is developed for a single-carrier (SC) modulation, which is suitable for reduced power consumption as compared to using OFDM modulation. However, the SC modulation is sensitive to in-band amplitude variation, mainly made worse by the gain variation of analog circuits and multipath delay spread. In order to compensate for those gain variations, the proposed chipset employs built-in TX in-band calibration and an RX frequency domain equalizer (FDE). The proposed techniques can relax the requirement for high speed analog circuits, leading to less power consumption while minimizing the increase of hardware size.

Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM

Abstract: Power issues have become a major problem of CMOS logic circuits as technology node shrinks below 90 nm. In order to overcome this limitation, emerging logic-in-memory architecture based on nonvolatile memories (NVMs) are being investigated. Spin transfer torque (STT) magnetic random access memory (MRAM) is considered one of the most promising NVMs thanks to its high speed, low power, good endurance, and 3-D back-end integration. This paper presents a novel magnetic full-adder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM. It provides advantageous power efficiency and die area compared with conventional CMOS-only full adder (FA). Transient simulations have been performed to validate this design by using an industrial CMOS 40 nm design kit and an accurate STT-MRAM compact model including physical models and experimental measurements.

Class-D CMOS Oscillators

Abstract: This paper presents class-D CMOS oscillators capable of an excellent phase noise performance from a very low power supply voltage. Starting from the recognition of the time-variant nature of the class-D LC tank, accurate expressions of the oscillation frequency, oscillation amplitude, current consumption, phase noise, and figure-of-merit (FoM) have been derived. Compared with the commonly used class-B/C architectures, the optimal class-D oscillator produces less phase noise for the same power consumption, at the expense of a higher power supply pushing. A prototype of a class-D voltage-controlled oscillator (VCO) targeted for mobile applications, implemented in a standard 65-nm CMOS process, covers a 46% tuning range between 3.0 and 4.8 GHz; drawing 10 mA from 0.4 V, the phase noise at 10-MHz offset from 4.8 GHz is -143.5 dBc/Hz, for an FoM of 191 dBc/Hz with less than 1-dB variation across the tuning range. A version of the same VCO with a resonant tail filter displays a lower 1/f3 phase-noise corner and improves the FoM by 1 dB.

A 0.45 V 100-Channel Neural-Recording IC With Sub- $\mu {\rm W}$ /Channel Consumption in 0.18 $\mu{\rm m}$ CMOS

Abstract: Neural prosthetics and personal healthcare have increasing need of high channel density low noise low power neural sensor interfaces. The input referred noise and quantization resolution are two essential factors which prevent conventional neural sensor interfaces from simultaneously achieving a good noise efficiency factor and low power consumption. In this paper, a neural recording architecture with dynamic range folding and current reuse techniques is proposed and dedicated to solving the noise and dynamic range trade-off under low voltage low power operation. Measured results from the silicon prototype show that the proposed design achieves 3.2 μVrms input referred noise and 8.27 effective number of bits at only 0.45 V supply and 0.94 μW/channel power consumption.

A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS

Abstract: In this paper, a 10b 0.5-to-4MS/s asynchronous SAR ADC is proposed and prototyped in 90nm CMOS. The supply voltage is scaled down appropriately (0.4 to 0.7V) for different speeds to minimize power consumption of SAR control and switching energy. Moreover, a charge average switching (CAS) DAC is developed to reduce the switching energy of the DAC without an extra voltage reference and common-mode shift. In near-threshold operation with a scaled-down supply, a double-boosted sample-and-hold (S/H) circuit and a local-boosted switch are implemented for the linearity and accuracy requirements of the 10b ADC.

A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

Abstract: A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.

A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS

Abstract: Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction.

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Abstract: This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple- V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

Abstract: This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 and 32. Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.

Ultralow Power, Fully Autonomous Boost Rectifier for Electromagnetic Energy Harvesters

Abstract: In this paper, a complete power conditioning system for a vibration energy harvester is presented that operates at ultralow power levels The power conditioning system, implemented with discrete components, is self-starting and fully autonomous, and based upon a full-wave boost rectifier topology The design utilizes the stray inductance of the harvester's coil, eliminating the need for separate inductors, and employs open-loop control that reduces the quiescent power overhead to just 21 μW, while still extracting 84% of the maximum available power from the harvester The design of the subsystems, including self-start circuitry, is described in detail, and it is shown that careful active device selection is required to minimize losses It is experimentally demonstrated that the power converter achieves conversion efficiencies of up to 76% at submilliwatt power levels, including quiescent losses The overall system efficiency peaks at 65% at 09 mW, while still achieving 51% at 200 μW The ability of this system to operate efficiently at ultralow average power levels opens up new possibilities to further miniaturize vibration harvesters and deploy them into environments with lower vibration levels than is currently possible

112Gb/s DP-QPSK transmission Over 2427km SSMF using small-size silicon photonic IQ modulator and low-power CMOS driver

Abstract: We report 2427km, 112Gb/s DP-QPSK optical transmission using the smallest Silicon Photonic modulator and lowest power CMOS MZM driver. BER characterization of this device demonstrates comparable performance relative to a commercial LiNbO3 modulator.

A 15-bit 140- $\mu$ W Scalable-Bandwidth Inverter-Based $\Delta \Sigma $ Modulator for a MEMS Microphone With Digital Output

Abstract: A discrete-time audio ΔΣ modulator for a MEMS microphone with digital output is presented that features a scalable signal bandwidth to also support ultrasonic frequencies for proximity sensing applications such as gesture recognition. The modulator achieves low power consumption and a small die area by using simple digital inverter instead of OTAs. To increase the robustness of the inverter approach, an LDO is used to provide an internally generated supply which regulates the inverter bias point. The LDO also improves the power supply rejection of the pseudo-differential architecture to above 78 dB. The presented ΔΣ modulator supports a scalable signal bandwidth up to 100 kHz, by dynamically adjusting the internal supply voltage depending on the sampling frequency. In the nominal 20-kHz audio band, it dissipates 140 μW from a minimum 1.5-V supply and achieves a DR of 92.6 dB , a SNDR of 87.9 dB, and a THD of -102.7 dB, respectively.

Steep switching tunnel FET: a promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications

Abstract: Steep switching Tunnel FETs (TFET) can extend the supply voltage scaling with improved energy efficiency for both digital and analog/RF application. In this paper, recent approaches on III-V Tunnel FET device design, prototype device demonstration, modeling techniques and performance evaluations for digital and analog/RF application are discussed and compared to CMOS technology. The impact of steep switching, uni-directional conduction and negative differential resistance characteristics are explored from circuit design perspective. Circuit-level implementation such as III-V TFET based Adder and SRAM design shows significant improvement on energy efficiency and power reduction below 0.3V for digital application. The analog/RF metric evaluation is presented including gm/Ids metric, temperature sensitivity, parasitic impact and noise performance. TFETs exhibit promising performance for high frequency, high sensitivity and ultra-low power RF rectifier application.

A Study on the Use of Performance Counters to Estimate Power in Microprocessors

Abstract: We present a study on estimating the dynamic power consumption of a processor based on performance counters. Today's processors feature a large number of such counters to monitor various CPU and memory parameters, such as utilization, occupancy, bandwidth, page, cache, and branch buffer hit rates. The use of various sets of performance counters to estimate the power consumed by the processor has been demonstrated in the past. Our goal is to find out whether there exists a subset of counters that can be used to estimate, with sufficient accuracy, the dynamic power consumption of processors with varying microarchitecture. To this end, we consider two recent processor configurations representing two extremes of the performance spectrum, one targeting low power and the other high performance. Our results indicate that only three counters measuring 1) the number of fetched instructions, 2) level-1 cache hits, and 3) dispatch stalls are sufficient to achieve adequate precision. These counters are shown to be effective in predicting the dynamic power consumption across processors of varying resource sizes achieving a prediction accuracy of 95%.

A 0.8-V 230- $\mu$ W 98-dB DR Inverter-Based $\Sigma \Delta$ Modulator for Audio Applications

Abstract: This paper presents a ΣΔ modulator based on a gain-boost class-C inverter for audio applications. The gain-boost class-C inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm 2. The experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230-μW power, which demonstrates that the gain-boost class-C inverter is particularly suitable for low-voltage micro-power high-resolution applications.

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

Abstract: A 162 Mb voltage-scalable SRAM array design in 22 nm CMOS tri-gate logic technology is presented. The designs of a 0.092 μm2 bitcell for high density applications and a 0.108 μm2 bitcell for improved performance at low supply voltage are introduced. Transient voltage collapse and wordline under-drive peripheral assist circuits improve low-voltage operating margins and address fin quantization. Co-optimization of tri-gate transistors and circuits allow up to 70% improvement in frequency at low voltages and 85% improvement in density from a scaled 32 nm design. The low-voltage array design demonstrates 4.6 GHz operation at 1.0 V and 3.4 GHz operation at 0.8 V while achieving array densities up to 6.7 Mb/mm2.

A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

Abstract: This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sampling front-end and a novel dynamic offset-modulation technique. The low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-amplifier (TIA) receivers. In addition, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160-μA current sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Optical measurements performed by a 1550-nm wire-bonded photodiode show better than - 4.7-dBm optical sensitivity at 24 Gb/s. The receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm2 silicon area.

Energy Efficient Low-Noise Multichannel Neural Amplifier in Submicron CMOS Process

Abstract: This paper presents a low noise low power neural recording amplifier that occupies a very small silicon area and is suitable to integrate with multielectrode arrays in cortical implants. We analyze main problems in neural recording systems processed in modern submicron technologies, i.e., leakage currents, ability to obtain very large and precisely controlled MOS based resistances and spread of the main system parameters from channel to channel. We also introduce methods allowing to mitigate them. Finally, we present methods allowing to calculate optimal channel dimensions of the recording channel's input transistors in order to obtain the lowest Input Referred Noise (IRN) for given power and area requirements. The proposed methodology has been applied in the 8-channel integrated recording ASIC dedicated to the broad range of neurobiology experiments. Each of the recording channels is equipped with the control register that enables to set main channel parameters independently. Thanks to this functionality, the user is capable of setting lower cut-off frequency within the range of 300 mHz-900 Hz. The upper cut-off frequency can be switched either to 30 Hz-290 Hz or 9 kHz, while the voltage gain can be set either to 260 V/V or 1000 V/V. A single recording channel is supplied with 1.8 V and consumes only 11 μW of power, while its input referred noise is equal to 4.4 μV resulting in NEF equal to 4.1.

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

Abstract: The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.

Feasibility study on ambient RF energy harvesting for wireless sensor network

Abstract: RF energy harvesting holds a promising future for generating a small amount of energy to potentially power on a low power device such as wireless sensor network especially in an urban country like Singapore Due to path loss and restriction on permissible transmission power; the RF power available to the input of the RF energy harvesting system is relative low In this work, we present a study of ambient RF energy harvesting We also explore to determine whether another emerging technology wireless power transfer can be integrated with RF energy harvesting A measurement of the ambient RF power density on GSM 900 and GSM 1800 bands in Nanyang Polytechnic of Singapore is presented From our conclusion, the harvested energy is not able to directly power the wireless sensor network; however the harvested energy can be stored in a super-capacitor and over some time it can be used to power on the wireless sensor network So, is RF energy harvesting ever going to become a practical reality? The answer is a cautious yes

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications

Abstract: This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.

Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic

Abstract: In this paper, we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in the precharge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull-down transistors. The DDFF offers a power reduction of up to 37% and 30% compared to the conventional flip-flops at 25% and 50% data activities, respectively. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a 90 nm UMC process show a power reduction of 27% compared to the Semidynamic flip-flop, with no degradation in speed performance. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs. Also, DDFF and DDFF-ELM are compared with other state-of-the-art designs by implementing a 4-b synchronous counter and a 4-b Johnson up-down counter. The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern.

A Low-Power Interface for Capacitive Sensors With PWM Output and Intrinsic Low Pass Characteristic

Abstract: A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subsequently demodulated and integrated over a clock period. The charge obtained in this way is then converted into the output pulse duration by an approach that includes an intrinsic tunable low pass function. The main non idealities are thoroughly investigated in order to provide useful design indications and evaluate the actual potentialities of the proposed circuit. The theoretical predictions are compared with experimental results obtained with a prototype, designed and fabricated using 0.32 μm CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025× 515 mm2 and is marked by a power consuption of 84 μW. The input capacitance range is 0-256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ppm/°C.

A 3-µW 868-MHz wake-up receiver with −83 dBm sensitivity and scalable data rate

Abstract: A ultra-low power wake-up receiver based on a novel fast sampling method is presented. The innovative approach allows the scalability of current consumption versus data rate at a constant sensitivity, meeting both short reaction time and ultra-low power consumption requirements. The 868 MHz OOK receiver comprises an analogue superheterodyne front-end and two digital 31 bit correlating decoders. It is fabricated in a 130 nm CMOS technology. The current consumption of the prototype is 1.2 μA at 2.5 volts supply voltage and a reaction time of 484 ms. The receiver sensitivity is -83 dBm thus obtaining a line-of-sight distance of 1200 metres for an assumed transmit power of 10 mW. Compared to other sub-100 μW receivers, the sensitivity of the presented implementation is best.

A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS

Abstract: Advanced human-machine interfaces require improved embedded sensors that can seamlessly interact with the user. Voice-based communication has emerged as a promising interface for next generation mobile, automotive and hands-free devices. Presented here is such an audio front-end with Voice Activity Detection (VAD) hardware targeted for low-power embedded SoCs, featuring a 512 pt FFT, programmable filters, noise floor estimator and a decision engine which has been fabricated in 32 nm CMOS. The dual-VCC, dual-frequency design allows the core datapath to scale to near-threshold voltage (NTV), where power consumption is less than 50 uW. At peak energy efficiency, the core can process audio data at 2.3 nJ/frame - a 9.4X improvement over nominal voltage conditions.

Charge steering: A low-power design paradigm

Abstract: Discrete-time charge-steering circuits consume less power than their continuous-time current-steering counterparts even at high speeds. This advantage can be exploited in the design of semi-analog circuits such as latches, demultiplexers, and CDR circuits as well as mixed-mode systems such as ADCs. Employing charge steering in 65-nm CMOS technology, a 25-Gb/s CDR/deserializer consumes 5 mW and a 10-bit 800-MHz pipelined ADC draws 19 mW.