Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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ACE: Automatic Centroid Extractor for real time target tracking
TL;DR: A high performance video image processor has been implemented which is capable of grouping contiguous pixels from a raster scan image into groups and then calculating centroid information for each object in a frame.
Proceedings ArticleDOI
A digital frequency synthesizer for a 2.4 GHz fast frequency hopping transceiver
R. Uusikartano,J. Niittylahti +1 more
TL;DR: The proposed architecture is compared to a traditional look-up based direct digital frequency synthesizer with similar performance and simulation and synthesis results for a VHDL-implementation of the architecture are given.
Proceedings ArticleDOI
Design and implementation of a high-speed reconfigurable multiplier
TL;DR: A high-speed reconfigurable multiplier is presented, which can be reconfigured to perform 16-bit, 32-bit multiplication and modulo 216+1 multiplication operation, and then optimize each critical block to achieve relatively high performance in the block cipher algorithms processing.
Journal ArticleDOI
Self-Timed Adaptive Digit-Serial Addition
Ned Bingham,Rajit Manohar +1 more
TL;DR: It is hypothesize that bit- or digit-serial implementations for arbitrary-length streams represent an opportunity to decrease the overall energy usage while increasing the throughput/area efficiency of the system and verify this hypothesis by constructing an asynchronous digit- serial adder for comparison against its bit-parallel counterparts.
Proceedings ArticleDOI
Parallel Prefix Polymorphism Permits Parallelization, Presentation a Proof
Jiahao Chen,Alan Edelman +1 more
TL;DR: It is shown that polymorphism has broad applicability far beyond computations for technical computing: parallelism in distributed computing, presentation of visualizations of runtime data flow, and proofs for formal verification of correctness.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.