Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL
TL;DR: The design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL) is presented, which allows constant resolution over process and temperatures spreads, avoids an off-chip filter and guarantees fast lock.
Journal ArticleDOI
On Modulo 2^n+1 Adder Design
TL;DR: The first architecture is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n+1 addition and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator.
Journal ArticleDOI
Power-delay characteristics of CMOS adders
TL;DR: It is shown that by sizing transistors judiciously it is possible to gain significant speed improvements at the cost of only a slight increase in power and hence a better power-delay product.
Proceedings ArticleDOI
Low power/energy BIST scheme for datapaths
TL;DR: This work proposes low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns, and finds that these schemes are more efficient than pseudorandom BIST for the same high fault coverage target.
Proceedings ArticleDOI
The Chinese Remainder Theorem and its application in a high-speed RSA crypto chip
TL;DR: The multiplier architecture of the RSA/spl gamma/ crypto-chip, a high-speed hardware accelerator for long-integer modular arithmetic, is presented, which increases the decryption rate by a factor of 3.5 to almost 2 Mbit/s.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.