Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Recursive implementation of optimal time VLSi integer multipliers
W. K. Luk,Jean Vuillemin +1 more
TL;DR: The first multiplier, although theoretical area-time suboptimal, is faster than all previously published ones for practical size, 16x16 and over, and it admits a reglular and compact program generated layout, and its area requirements are well within the possibilities of current technologies.
Proceedings ArticleDOI
A pipeline FFT processor
Weidong Li,L. Wanhammar +1 more
TL;DR: This work discusses the design and implementation of a high-speed, low power 1024-point pipeline FFT processor, which is efficient in terms of power consumption and chip area.
Journal ArticleDOI
High-performance carry chains for FPGA's
Scott Hauck,M.M. Hosler,T.W. Fry +2 more
TL;DR: This paper demonstrates how more advanced carry constructs can be embedded into PPGA's, providing significantly higher performance carry computations, and redesigns the standard ripple carry chain to reduce the number of logic levels in each cell.
Proceedings ArticleDOI
Performance of Parallel Prefix Adders implemented with FPGA technology
TL;DR: This paper investigates the performance of parallel prefixAdders implemented with FPGA technology and reports on the area requirements and critical path delay for a variety of classical parallel prefix adder structures.
Journal ArticleDOI
Synaptic plasticity in spiking neural networks (SP/sup 2/INN): a system approach
TL;DR: The configurable neuron model of SP/sup 2/INN, a digital system for simulating very large-scale spiking neural networks (VLSNNs) comprising, e.g., 1000000 neurons with several million connections in total, is described and the computation of the connectivity is handled efficiently.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.