Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Journal ArticleDOI
VLSI implementations of efficient isotropic flexible 2D convolvers
TL;DR: A new 2D isotropic convolver designed to operate on 256 grey-level images is presented, and when realised by using 90 nm IV CMOS technology, exhibits a 1.25-GHz running frequency with an average power dissipation of only sime1 mW/MHz.
Proceedings ArticleDOI
A folded 32-bit prefix tree adder in 0.16-/spl mu/m static CMOS
TL;DR: A new prefix tree adder that is faster than previously published adder designs is presented, achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries are generated.
Proceedings ArticleDOI
Power-speed trade-off in parallel prefix circuits
TL;DR: A comparative study of different parallel prefix circuits form the point of view of power-speed trade-off can help identify parallel prefix algorithms with the desirable power consumption with a given throughput.
Computer-aided-design methods for emerging quantum computing technologies
TL;DR: A novel QMDD-based tool for cascade logic synthesis that utilizes the Q MDD minimized variable order for lexicographical synthesis with garbage minimization included as an optimization criterion and a synthesis tool that investigates the QCA native 3-input majority gates ability to implement complex logic circuits.
Dissertation
Design of Low-Power Reduction-Trees in Parallel Multipliers
TL;DR: Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.