Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Time-Optimal Design of a CMOS Adder
TL;DR: This paper defines a family of adders, based on a modular design, and formulate the adder design as a dynamic programming problem, optimizing with respect to time, and has found the fastest 32-bit CMOS adder in this design family.
Proceedings ArticleDOI
Pipelining saturated accumulation
TL;DR: This work shows how to reformulate saturated addition as an associative operation so that it can be used as a parallel-prefix calculation to perform saturated accumulation at any data rate supported by the device.
Proceedings ArticleDOI
Low power tradeoffs in signal processing hardware primitives
TL;DR: In this paper, extensive simulation results for different types of parallel adders, which are the most frequently used primitives in digital signal processing, are presented.
Proceedings ArticleDOI
Design and Performance Comparison among Various types of Adder Topologies
TL;DR: This paper has presented the implementation of various 16bit adder architectures of Ripple Carry Adder, Carry Lookahead Adder and Carry Skip Adder including parallel prefix adders and the comparative analysis of different adders has performed with respect to the performance parameters – area, delay and power.
Proceedings ArticleDOI
Bit-slice logic interleaving for spatial multi-bit soft-error tolerance
TL;DR: A new fault model is explored and the effectiveness of conventional fault tolerance techniques to mitigate spatial multi-bit error mitigation in logic is evaluated using a case study of a Brent-Kung adder at a 90-nm process.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.