Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Proceedings ArticleDOI
Algebraic Recurrence Transformations For Massive Parallelism
Gerhard Fettweis,Lothar Thiele +1 more
TL;DR: This paper shows that certain algebraic structures are sufficient for the operations of the loop, to allow the application of the well-knwn look-ahead computation, which provides a unifying algebraic hasis to derive a new generalization for more complex recursions with more than one operation.
Journal ArticleDOI
Optimal VLSI complexity design for high speed pipeline FFT using RNS
Giuseppe Alia,Enrico Martinelli +1 more
TL;DR: A logic design, based on RNS units, to perform the N point FFT on a continuous data stream is proposed, and its performance is evaluated in terms of asymptotic VLSI complexity.
Journal Article
Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product
P. Ramanathan,P. T. Vanathi +1 more
TL;DR: A new architecture for performing 8-bit, 16-bit and 32-bit Parallel Prefix addition is proposed and it is revealed that the proposed structures have the least power delay product when compared with its peer existing Prefix adder structures.
Proceedings ArticleDOI
High Performance Low-Power Sparse-Tree Binary Adders
TL;DR: A new conception called performance-vector is proposed in this paper to measure the performance of prefix adders, and a kind of high performance low-power prefix adder with sparse-tree architecture is introduced.
Parallel systems in symbolic and algebraic computation
TL;DR: This thesis describes techniques that exploit the distributed memory in massively parallel processors to satisfy the peak memory requirements of some very large computer algebra problems and demonstrates that careful attention to memory management aids solution of very large problems even without the benefit of advanced algorithms.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.