Journal ArticleDOI
A Regular Layout for Parallel Adders
TLDR
It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.Abstract:
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.read more
Citations
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Book Chapter
A Structured Approach to VLSI Layout Design
TL;DR: A new approach to the VLSI layout problem is proposed that produces a structured floor plan for an arbitrary network of interconnected processing elements based on extracting a minimum spanning tree from a given representation of a computation network and using an efficient, structured layout scheme for thisminimum spanning tree.
Proceedings ArticleDOI
On the implementation of an efficient performance driven generator for conditional-sum-adders
TL;DR: The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adder of the conditional-sum type with delay /spl les/t/sub n/, if such a circuit exists.
A High-Speed Realization of Chinese Remainder Theorem
Shuangching Chen,Shugang Wei +1 more
TL;DR: A novel technique for the Chinese remainder theorem (CRT) with the moduli (2 n i 1,2 n ,2 n +1) is proposed and the computation time is shorten by 34%.
Proceedings ArticleDOI
Design and performance evaluation of Hybrid Prefix Adder and carry increment adder in 90nm regime
A. N. Nagamani,B.K. Shivanand +1 more
TL;DR: An implementation of two 8-bit adders (HPA and CIA) and comparing their performance with respect to power delay product for different voltages in 90 nm regime is presented.
Proceedings ArticleDOI
VLSI implementation of a 32-bit Kozen formulation Ladner/Fischer parallel prefix adder
K.J. Janik,Shih-Lien Lu +1 more
TL;DR: The parallel prefix adder is ideally suited for use in VLSI applications because it has a regular structure with very limited fan-out and has depth O(log n) and area O(n).
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
Parallel Prefix Computation
TL;DR: A recurstve construction is used to obtain a product circuit for solving the prefix problem and a Boolean clrcmt which has depth 2[Iog2n] + 2 and size bounded by 14n is obtained for n-bit binary addmon.